VIRGO: Hierarchical DSP Code Generator Based on Vectorized Signal Flow Graph Description
Summary :
This paper proposes a hierarchical Digital Signal Processor (DSP) Code Generator VIRGO for large scale general signal processing algorithms. Hierarchical structured Vectorized Signal Flow Graph (V-SFG) description is used as input specifications. Ths DSP independent optimization procedure for both the program size and the execution time is performed each module by each hierarchically with regard to operation order, memory assignment and register allocation. The efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical ADPCM encoder/decoder with a conventional method.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E75-A No.8 pp.1004-1013
- Publication Date
- 1992/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on the 6th Digital Signal Processing Symposium)
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Norichika KUMAMOTO, Keiji AOKI, Hiroaki KUNIEDA, "VIRGO: Hierarchical DSP Code Generator Based on Vectorized Signal Flow Graph Description" in IEICE TRANSACTIONS on Fundamentals,
vol. E75-A, no. 8, pp. 1004-1013, August 1992, doi: .
Abstract: This paper proposes a hierarchical Digital Signal Processor (DSP) Code Generator VIRGO for large scale general signal processing algorithms. Hierarchical structured Vectorized Signal Flow Graph (V-SFG) description is used as input specifications. Ths DSP independent optimization procedure for both the program size and the execution time is performed each module by each hierarchically with regard to operation order, memory assignment and register allocation. The efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical ADPCM encoder/decoder with a conventional method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e75-a_8_1004/_p
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@ARTICLE{e75-a_8_1004,
author={Norichika KUMAMOTO, Keiji AOKI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VIRGO: Hierarchical DSP Code Generator Based on Vectorized Signal Flow Graph Description},
year={1992},
volume={E75-A},
number={8},
pages={1004-1013},
abstract={This paper proposes a hierarchical Digital Signal Processor (DSP) Code Generator VIRGO for large scale general signal processing algorithms. Hierarchical structured Vectorized Signal Flow Graph (V-SFG) description is used as input specifications. Ths DSP independent optimization procedure for both the program size and the execution time is performed each module by each hierarchically with regard to operation order, memory assignment and register allocation. The efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical ADPCM encoder/decoder with a conventional method.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - VIRGO: Hierarchical DSP Code Generator Based on Vectorized Signal Flow Graph Description
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1004
EP - 1013
AU - Norichika KUMAMOTO
AU - Keiji AOKI
AU - Hiroaki KUNIEDA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 1992
AB - This paper proposes a hierarchical Digital Signal Processor (DSP) Code Generator VIRGO for large scale general signal processing algorithms. Hierarchical structured Vectorized Signal Flow Graph (V-SFG) description is used as input specifications. Ths DSP independent optimization procedure for both the program size and the execution time is performed each module by each hierarchically with regard to operation order, memory assignment and register allocation. The efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical ADPCM encoder/decoder with a conventional method.
ER -
English
