IEICE TRANSACTIONS on Fundamentals
A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System
Summary :
A hardware accelerator for a raster-based design-rule checking called BITDRC for a bit-mapping CAD system is described. BITDRC is a special-purpose hardware accelerator which performs design-rule checking for the Manhattan layout style VLSI circuis, much faster than the software checking which belonged to the bit-mapping CAD system before. The bit-mapping CAD system had effectively been developed for both of educational and VLSI design purposes, and just needs only a personal computer as a compact working environment. The proposed hardware architecture is rather simply and characterized by the bit-mapping CAD system where it works on. The hardware architecture and checking algorithm have been confirmed by implementing a bread-board prototype using discrete components. As a result, the processing time of BITDRC is speeded up as much as 500 times faster than the original software and takes only 4 seconds for checking every rule on a(1500
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.10 pp.1684-1693
- Publication Date
- 1993/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Cong-Kha PHAM, Katsufusa SHONO, "A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System" in IEICE TRANSACTIONS on Fundamentals,
vol. E76-A, no. 10, pp. 1684-1693, October 1993, doi: .
Abstract: A hardware accelerator for a raster-based design-rule checking called BITDRC for a bit-mapping CAD system is described. BITDRC is a special-purpose hardware accelerator which performs design-rule checking for the Manhattan layout style VLSI circuis, much faster than the software checking which belonged to the bit-mapping CAD system before. The bit-mapping CAD system had effectively been developed for both of educational and VLSI design purposes, and just needs only a personal computer as a compact working environment. The proposed hardware architecture is rather simply and characterized by the bit-mapping CAD system where it works on. The hardware architecture and checking algorithm have been confirmed by implementing a bread-board prototype using discrete components. As a result, the processing time of BITDRC is speeded up as much as 500 times faster than the original software and takes only 4 seconds for checking every rule on a(1500
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e76-a_10_1684/_p
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@ARTICLE{e76-a_10_1684,
author={Cong-Kha PHAM, Katsufusa SHONO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System},
year={1993},
volume={E76-A},
number={10},
pages={1684-1693},
abstract={A hardware accelerator for a raster-based design-rule checking called BITDRC for a bit-mapping CAD system is described. BITDRC is a special-purpose hardware accelerator which performs design-rule checking for the Manhattan layout style VLSI circuis, much faster than the software checking which belonged to the bit-mapping CAD system before. The bit-mapping CAD system had effectively been developed for both of educational and VLSI design purposes, and just needs only a personal computer as a compact working environment. The proposed hardware architecture is rather simply and characterized by the bit-mapping CAD system where it works on. The hardware architecture and checking algorithm have been confirmed by implementing a bread-board prototype using discrete components. As a result, the processing time of BITDRC is speeded up as much as 500 times faster than the original software and takes only 4 seconds for checking every rule on a(1500
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1684
EP - 1693
AU - Cong-Kha PHAM
AU - Katsufusa SHONO
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1993
AB - A hardware accelerator for a raster-based design-rule checking called BITDRC for a bit-mapping CAD system is described. BITDRC is a special-purpose hardware accelerator which performs design-rule checking for the Manhattan layout style VLSI circuis, much faster than the software checking which belonged to the bit-mapping CAD system before. The bit-mapping CAD system had effectively been developed for both of educational and VLSI design purposes, and just needs only a personal computer as a compact working environment. The proposed hardware architecture is rather simply and characterized by the bit-mapping CAD system where it works on. The hardware architecture and checking algorithm have been confirmed by implementing a bread-board prototype using discrete components. As a result, the processing time of BITDRC is speeded up as much as 500 times faster than the original software and takes only 4 seconds for checking every rule on a(1500
ER -
English
