We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time–first method, the time needed for each gate evaluation is not given beforehand, and is not constant. This feature distinguishes the processor scheduling problem from typical task scheduling problems. First, we devise newly Algorithm MET to solve the processor scheduling problem. The key idea of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well–known twelve benchmark combinational circuits show the usefulness of Algorithm, MET, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinational circuits.
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Tadashi SEKO, Tohru KIKUNO, "Experimental Evaluation of Dynamic Scheduling for Parallel Logic Simulation Using Benchmark Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E77-A, no. 11, pp. 1910-1912, November 1994, doi: .
Abstract: We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time–first method, the time needed for each gate evaluation is not given beforehand, and is not constant. This feature distinguishes the processor scheduling problem from typical task scheduling problems. First, we devise newly Algorithm MET to solve the processor scheduling problem. The key idea of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well–known twelve benchmark combinational circuits show the usefulness of Algorithm, MET, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinational circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e77-a_11_1910/_p
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@ARTICLE{e77-a_11_1910,
author={Tadashi SEKO, Tohru KIKUNO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Experimental Evaluation of Dynamic Scheduling for Parallel Logic Simulation Using Benchmark Circuits},
year={1994},
volume={E77-A},
number={11},
pages={1910-1912},
abstract={We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time–first method, the time needed for each gate evaluation is not given beforehand, and is not constant. This feature distinguishes the processor scheduling problem from typical task scheduling problems. First, we devise newly Algorithm MET to solve the processor scheduling problem. The key idea of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well–known twelve benchmark combinational circuits show the usefulness of Algorithm, MET, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinational circuits.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Experimental Evaluation of Dynamic Scheduling for Parallel Logic Simulation Using Benchmark Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1910
EP - 1912
AU - Tadashi SEKO
AU - Tohru KIKUNO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1994
AB - We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time–first method, the time needed for each gate evaluation is not given beforehand, and is not constant. This feature distinguishes the processor scheduling problem from typical task scheduling problems. First, we devise newly Algorithm MET to solve the processor scheduling problem. The key idea of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well–known twelve benchmark combinational circuits show the usefulness of Algorithm, MET, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinational circuits.
ER -