A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
Summary :
This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.12 pp.2053-2057
- Publication Date
- 1994/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
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Tetsushi KOIDE, Yoshinori KATSURA, Katsumi YAMATANI, Shin'ichi WAKABAYASHI, Noriyoshi YOSHIDA, "A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout" in IEICE TRANSACTIONS on Fundamentals,
vol. E77-A, no. 12, pp. 2053-2057, December 1994, doi: .
Abstract: This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e77-a_12_2053/_p
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@ARTICLE{e77-a_12_2053,
author={Tetsushi KOIDE, Yoshinori KATSURA, Katsumi YAMATANI, Shin'ichi WAKABAYASHI, Noriyoshi YOSHIDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout},
year={1994},
volume={E77-A},
number={12},
pages={2053-2057},
abstract={This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2053
EP - 2057
AU - Tetsushi KOIDE
AU - Yoshinori KATSURA
AU - Katsumi YAMATANI
AU - Shin'ichi WAKABAYASHI
AU - Noriyoshi YOSHIDA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1994
AB - This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.
ER -
English
