A Multi-Layer Channel Router Using Simulated Annealing

Masahiko TOYONAGA; Chie IWASAKI; Yoshiaki SAWADA; Toshiro AKINO

A Multi-Layer Channel Router Using Simulated Annealing

Masahiko TOYONAGA, Chie IWASAKI, Yoshiaki SAWADA, Toshiro AKINO

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We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.12 pp.2085-2091

Publication Date: 1994/12/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Masahiko TOYONAGA, Chie IWASAKI, Yoshiaki SAWADA, Toshiro AKINO, "A Multi-Layer Channel Router Using Simulated Annealing" in IEICE TRANSACTIONS on Fundamentals, vol. E77-A, no. 12, pp. 2085-2091, December 1994, doi: .
Abstract: We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e77-a_12_2085/_p

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@ARTICLE{e77-a_12_2085,
author={Masahiko TOYONAGA, Chie IWASAKI, Yoshiaki SAWADA, Toshiro AKINO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Multi-Layer Channel Router Using Simulated Annealing},
year={1994},
volume={E77-A},
number={12},
pages={2085-2091},
abstract={We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Multi-Layer Channel Router Using Simulated Annealing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2085
EP - 2091
AU - Masahiko TOYONAGA
AU - Chie IWASAKI
AU - Yoshiaki SAWADA
AU - Toshiro AKINO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1994
AB - We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.
ER -