Petri Nets-Based Super Scalar Computing in Programmable Controllers
Summary :
This paper proposes a hardware architecture of programmable controller based on Petri nets. The suggested architecture achieves sufficiently rapid processing even as demands on PCs become increasingly more complex. The architecture's speed and efficiency are derived from an automatic and dynamic super scalar computing capability that executes bit instructions and data handling instructions simultaneously without preprocessing, due to the properties of Petri nets. Specific characteristics for both architectural memory-based implementation of Petri nets and evolution algorithms are suggested and classified by the net structure. Analysis of the suggested architectures and effects on performance are also given with mathematical formulas and a computer simulation.
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- IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.11 pp.1511-1518
- Publication Date
- 1995/11/25
- Publicized
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- Type of Manuscript
- Special Section PAPER (Special Section on Net Theory and Its Applications to Discrete Event System Design)
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Naehyuck GHANG, Jaehyun PARK, Wook Hyun KWON, "Petri Nets-Based Super Scalar Computing in Programmable Controllers" in IEICE TRANSACTIONS on Fundamentals,
vol. E78-A, no. 11, pp. 1511-1518, November 1995, doi: .
Abstract: This paper proposes a hardware architecture of programmable controller based on Petri nets. The suggested architecture achieves sufficiently rapid processing even as demands on PCs become increasingly more complex. The architecture's speed and efficiency are derived from an automatic and dynamic super scalar computing capability that executes bit instructions and data handling instructions simultaneously without preprocessing, due to the properties of Petri nets. Specific characteristics for both architectural memory-based implementation of Petri nets and evolution algorithms are suggested and classified by the net structure. Analysis of the suggested architectures and effects on performance are also given with mathematical formulas and a computer simulation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_11_1511/_p
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@ARTICLE{e78-a_11_1511,
author={Naehyuck GHANG, Jaehyun PARK, Wook Hyun KWON, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Petri Nets-Based Super Scalar Computing in Programmable Controllers},
year={1995},
volume={E78-A},
number={11},
pages={1511-1518},
abstract={This paper proposes a hardware architecture of programmable controller based on Petri nets. The suggested architecture achieves sufficiently rapid processing even as demands on PCs become increasingly more complex. The architecture's speed and efficiency are derived from an automatic and dynamic super scalar computing capability that executes bit instructions and data handling instructions simultaneously without preprocessing, due to the properties of Petri nets. Specific characteristics for both architectural memory-based implementation of Petri nets and evolution algorithms are suggested and classified by the net structure. Analysis of the suggested architectures and effects on performance are also given with mathematical formulas and a computer simulation.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Petri Nets-Based Super Scalar Computing in Programmable Controllers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1511
EP - 1518
AU - Naehyuck GHANG
AU - Jaehyun PARK
AU - Wook Hyun KWON
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1995
AB - This paper proposes a hardware architecture of programmable controller based on Petri nets. The suggested architecture achieves sufficiently rapid processing even as demands on PCs become increasingly more complex. The architecture's speed and efficiency are derived from an automatic and dynamic super scalar computing capability that executes bit instructions and data handling instructions simultaneously without preprocessing, due to the properties of Petri nets. Specific characteristics for both architectural memory-based implementation of Petri nets and evolution algorithms are suggested and classified by the net structure. Analysis of the suggested architectures and effects on performance are also given with mathematical formulas and a computer simulation.
ER -
English
