IEICE TRANSACTIONS on Fundamentals
Phase Optimization in Technology Mapping
Summary :
Though tree covering is an efficient algorithm for technology mapping, phase assignments on tree boundaries are not taken into consideration. Several inverter minimization algorithms have been proposed so far, but they do phase optimization before or after technology mapping, and their cost function is not to minimize the total area but to minimize the number of inverters. This paper describes a new formulation of phase optimization problem aiming to minimize the total area during the technology mapping. Cost function representing area according to each phase assignment is introduced, and tree covering algorithm is modified to handle that cost function. Edge-Valued Binary Decision Diagram is used to represent the function implicitly. Experimental results show that proposed method reduces about 10% area on average compared with a state-of-the-art logic synthesis system sis.
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- IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.12 pp.1735-1741
- Publication Date
- 1995/12/25
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Yusuke MATSUNAGA, "Phase Optimization in Technology Mapping" in IEICE TRANSACTIONS on Fundamentals,
vol. E78-A, no. 12, pp. 1735-1741, December 1995, doi: .
Abstract: Though tree covering is an efficient algorithm for technology mapping, phase assignments on tree boundaries are not taken into consideration. Several inverter minimization algorithms have been proposed so far, but they do phase optimization before or after technology mapping, and their cost function is not to minimize the total area but to minimize the number of inverters. This paper describes a new formulation of phase optimization problem aiming to minimize the total area during the technology mapping. Cost function representing area according to each phase assignment is introduced, and tree covering algorithm is modified to handle that cost function. Edge-Valued Binary Decision Diagram is used to represent the function implicitly. Experimental results show that proposed method reduces about 10% area on average compared with a state-of-the-art logic synthesis system sis.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_12_1735/_p
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@ARTICLE{e78-a_12_1735,
author={Yusuke MATSUNAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Phase Optimization in Technology Mapping},
year={1995},
volume={E78-A},
number={12},
pages={1735-1741},
abstract={Though tree covering is an efficient algorithm for technology mapping, phase assignments on tree boundaries are not taken into consideration. Several inverter minimization algorithms have been proposed so far, but they do phase optimization before or after technology mapping, and their cost function is not to minimize the total area but to minimize the number of inverters. This paper describes a new formulation of phase optimization problem aiming to minimize the total area during the technology mapping. Cost function representing area according to each phase assignment is introduced, and tree covering algorithm is modified to handle that cost function. Edge-Valued Binary Decision Diagram is used to represent the function implicitly. Experimental results show that proposed method reduces about 10% area on average compared with a state-of-the-art logic synthesis system sis.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Phase Optimization in Technology Mapping
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1735
EP - 1741
AU - Yusuke MATSUNAGA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1995
AB - Though tree covering is an efficient algorithm for technology mapping, phase assignments on tree boundaries are not taken into consideration. Several inverter minimization algorithms have been proposed so far, but they do phase optimization before or after technology mapping, and their cost function is not to minimize the total area but to minimize the number of inverters. This paper describes a new formulation of phase optimization problem aiming to minimize the total area during the technology mapping. Cost function representing area according to each phase assignment is introduced, and tree covering algorithm is modified to handle that cost function. Edge-Valued Binary Decision Diagram is used to represent the function implicitly. Experimental results show that proposed method reduces about 10% area on average compared with a state-of-the-art logic synthesis system sis.
ER -
English
