A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size

Shinsuke OHNO, Masao SATO, Tatsuo OHTSUKI

Summary :

CAMs (Content Addressable Memories) are functional memories which have functions such as word-parallel equivalence search, bilateral 1-bit data shifting between consecutive words, and word-parallel writing. Since CAMs can be integrated because of their regular structure, massively parallel CAM functions can be executed. Taking advantage of CAMs, Ishiura and Yajima have proposed a parallel fault simulation algorithm using a CAM. This algorithm, however, requires a large amount of CAM storage to simulate large-scale circuits. In this paper, we propose a new massively parallel fault simulation algorithm requiring less CAM storage, and compare it with Ishiura and Yajima's algorithm. Experimental results of the algorithm on CHARGE --the CAM-based hardware engine developed in our laboratory--are also reported.

• Publication: IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.12 pp.1755-1764
• Publication Date: 1995/12/25
• Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Authors

Shinsuke OHNO
Masao SATO
Tatsuo OHTSUKI

Keyword

Content Addressable Memory (CAM),  parallel fault simulation,  bit reusing strategy,  pipeline propagation,  hardware engine