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Mincut Partitioning Acceleration Using Hardware CAD Accelerator TP5000

Masahiro SANO, Shintaro SHIMOGORI, Fumiyasu HIROSE

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This paper presents a new approach of data pipelining for mincut partitioning acceleration using a parallel computer. When using a parallel computer, it is important to have many processors always active, also the quality of the partitioning must not be sacrificed. Out approach covers both speed and quality. We choose the hardware CAD accelerator TP5000 to implement our approach, which consists of dedicated Very Long Instruction Word (VLIW) processors with high-speed interconnections. The TP5000 allows its connections to be reconfigured to optimize the data pipelines. We estimate that the speed of our approach using 10 processors on the TP5000 is 30 times faster than a SPARCStation-10.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.12 pp.1785-1792
Publication Date
1995/12/25
Publicized
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DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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