IEICE TRANSACTIONS on Fundamentals
A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping
Summary :
Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.
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- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.10 pp.1813-1819
- Publication Date
- 1997/10/25
- Publicized
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Jie-Hong JIANG, Jing-Yang JOU, Juinn-Dar HUANG, Jung-Shian WEI, "A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 10, pp. 1813-1819, October 1997, doi: .
Abstract: Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_10_1813/_p
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@ARTICLE{e80-a_10_1813,
author={Jie-Hong JIANG, Jing-Yang JOU, Juinn-Dar HUANG, Jung-Shian WEI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping},
year={1997},
volume={E80-A},
number={10},
pages={1813-1819},
abstract={Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1813
EP - 1819
AU - Jie-Hong JIANG
AU - Jing-Yang JOU
AU - Juinn-Dar HUANG
AU - Jung-Shian WEI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1997
AB - Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.
ER -
English
