In this paper, we will show some significant results of the routability analysis of bit-serial pipeline datapath designs based on Rent's rule and Donath's observation. Our results show that all of the tested bit-serial benchmarks have Rent exponent of below 0.4, indicating that the average wiring length of the circuit is expected to be independent of the circuit size. This study provides some important implications on the silicon utilization and time-area efficiency of bit-serial pipeline circuits on FPGAs and ASICs.
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Tsuyoshi ISSHIKI, Wayne Wei-Ming DAI, Hiroaki KUNIEDA, "Routability Analysis of Bit-Serial Pipeline Datapaths" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 10, pp. 1861-1870, October 1997, doi: .
Abstract: In this paper, we will show some significant results of the routability analysis of bit-serial pipeline datapath designs based on Rent's rule and Donath's observation. Our results show that all of the tested bit-serial benchmarks have Rent exponent of below 0.4, indicating that the average wiring length of the circuit is expected to be independent of the circuit size. This study provides some important implications on the silicon utilization and time-area efficiency of bit-serial pipeline circuits on FPGAs and ASICs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_10_1861/_p
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@ARTICLE{e80-a_10_1861,
author={Tsuyoshi ISSHIKI, Wayne Wei-Ming DAI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Routability Analysis of Bit-Serial Pipeline Datapaths},
year={1997},
volume={E80-A},
number={10},
pages={1861-1870},
abstract={In this paper, we will show some significant results of the routability analysis of bit-serial pipeline datapath designs based on Rent's rule and Donath's observation. Our results show that all of the tested bit-serial benchmarks have Rent exponent of below 0.4, indicating that the average wiring length of the circuit is expected to be independent of the circuit size. This study provides some important implications on the silicon utilization and time-area efficiency of bit-serial pipeline circuits on FPGAs and ASICs.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Routability Analysis of Bit-Serial Pipeline Datapaths
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1861
EP - 1870
AU - Tsuyoshi ISSHIKI
AU - Wayne Wei-Ming DAI
AU - Hiroaki KUNIEDA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1997
AB - In this paper, we will show some significant results of the routability analysis of bit-serial pipeline datapath designs based on Rent's rule and Donath's observation. Our results show that all of the tested bit-serial benchmarks have Rent exponent of below 0.4, indicating that the average wiring length of the circuit is expected to be independent of the circuit size. This study provides some important implications on the silicon utilization and time-area efficiency of bit-serial pipeline circuits on FPGAs and ASICs.
ER -