IEICE TRANSACTIONS on Fundamentals
A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells
Summary :
We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.10 pp.1883-1891
- Publication Date
- 1997/10/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Shunji SAIKA, Masahiro FUKUI, Noriko SHINOMIYA, Toshiro AKINO, Shigeo KUNINOBU, "A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 10, pp. 1883-1891, October 1997, doi: .
Abstract: We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_10_1883/_p
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@ARTICLE{e80-a_10_1883,
author={Shunji SAIKA, Masahiro FUKUI, Noriko SHINOMIYA, Toshiro AKINO, Shigeo KUNINOBU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells},
year={1997},
volume={E80-A},
number={10},
pages={1883-1891},
abstract={We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1883
EP - 1891
AU - Shunji SAIKA
AU - Masahiro FUKUI
AU - Noriko SHINOMIYA
AU - Toshiro AKINO
AU - Shigeo KUNINOBU
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1997
AB - We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.
ER -
English
