IEICE TRANSACTIONS on Fundamentals
Instruction Sequence Based Synthesis for Application Specific Micro-Architecture
Summary :
In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.6 pp.1021-1032
- Publication Date
- 1997/06/25
- Publicized
- Online ISSN
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- Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
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Kyung-Sik JANG, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, "Instruction Sequence Based Synthesis for Application Specific Micro-Architecture" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 6, pp. 1021-1032, June 1997, doi: .
Abstract: In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_6_1021/_p
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@ARTICLE{e80-a_6_1021,
author={Kyung-Sik JANG, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Instruction Sequence Based Synthesis for Application Specific Micro-Architecture},
year={1997},
volume={E80-A},
number={6},
pages={1021-1032},
abstract={In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Instruction Sequence Based Synthesis for Application Specific Micro-Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1021
EP - 1032
AU - Kyung-Sik JANG
AU - Tsuyoshi ISSHIKI
AU - Hiroaki KUNIEDA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1997
AB - In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.
ER -
English
