IEICE TRANSACTIONS on Fundamentals
A New Approach for Datapath Synthesis of Application Specific Instruction Processor
Summary :
In this paper, a systematic method which synthesizes the datapath of Application Specific Instruction Processor (ASIP) is proposed. The behavioral description of application is written in instruction code defined on abstract machine. We introduce register transfer graph (RTG) to represent instructions and synthesis constraint tree to select the combinations of synthesis constraints to explore design space along area and performance axis. The high performance is achieved by scheduling micro-operations of instruction in out-of-order. The practical datapath is synthesized by considering connection geometry as well as the maximum utilization of hardware resources. To reduce connection cost, data transfer paths are minimized by replacing an inefficient data transfer path with its bypass route. The feasibility of the proposed synthesis method is verified with several experimental instruction sequences.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.8 pp.1478-1488
- Publication Date
- 1997/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- VLSI Design Technology and CAD
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Kyung-Sik JANG, Hiroaki KUNIEDA, "A New Approach for Datapath Synthesis of Application Specific Instruction Processor" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 8, pp. 1478-1488, August 1997, doi: .
Abstract: In this paper, a systematic method which synthesizes the datapath of Application Specific Instruction Processor (ASIP) is proposed. The behavioral description of application is written in instruction code defined on abstract machine. We introduce register transfer graph (RTG) to represent instructions and synthesis constraint tree to select the combinations of synthesis constraints to explore design space along area and performance axis. The high performance is achieved by scheduling micro-operations of instruction in out-of-order. The practical datapath is synthesized by considering connection geometry as well as the maximum utilization of hardware resources. To reduce connection cost, data transfer paths are minimized by replacing an inefficient data transfer path with its bypass route. The feasibility of the proposed synthesis method is verified with several experimental instruction sequences.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_8_1478/_p
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@ARTICLE{e80-a_8_1478,
author={Kyung-Sik JANG, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Approach for Datapath Synthesis of Application Specific Instruction Processor},
year={1997},
volume={E80-A},
number={8},
pages={1478-1488},
abstract={In this paper, a systematic method which synthesizes the datapath of Application Specific Instruction Processor (ASIP) is proposed. The behavioral description of application is written in instruction code defined on abstract machine. We introduce register transfer graph (RTG) to represent instructions and synthesis constraint tree to select the combinations of synthesis constraints to explore design space along area and performance axis. The high performance is achieved by scheduling micro-operations of instruction in out-of-order. The practical datapath is synthesized by considering connection geometry as well as the maximum utilization of hardware resources. To reduce connection cost, data transfer paths are minimized by replacing an inefficient data transfer path with its bypass route. The feasibility of the proposed synthesis method is verified with several experimental instruction sequences.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A New Approach for Datapath Synthesis of Application Specific Instruction Processor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1478
EP - 1488
AU - Kyung-Sik JANG
AU - Hiroaki KUNIEDA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 1997
AB - In this paper, a systematic method which synthesizes the datapath of Application Specific Instruction Processor (ASIP) is proposed. The behavioral description of application is written in instruction code defined on abstract machine. We introduce register transfer graph (RTG) to represent instructions and synthesis constraint tree to select the combinations of synthesis constraints to explore design space along area and performance axis. The high performance is achieved by scheduling micro-operations of instruction in out-of-order. The practical datapath is synthesized by considering connection geometry as well as the maximum utilization of hardware resources. To reduce connection cost, data transfer paths are minimized by replacing an inefficient data transfer path with its bypass route. The feasibility of the proposed synthesis method is verified with several experimental instruction sequences.
ER -
English
