This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.
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Masahiro FUKUI, Masakazu TANAKA, Masaharu IMAI, "Design Optimization by Using Flexible Pipelined Modules" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2521-2528, December 1998, doi: .
Abstract: This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2521/_p
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@ARTICLE{e81-a_12_2521,
author={Masahiro FUKUI, Masakazu TANAKA, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design Optimization by Using Flexible Pipelined Modules},
year={1998},
volume={E81-A},
number={12},
pages={2521-2528},
abstract={This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Design Optimization by Using Flexible Pipelined Modules
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2521
EP - 2528
AU - Masahiro FUKUI
AU - Masakazu TANAKA
AU - Masaharu IMAI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.
ER -