Internet-Based Hierarchical Floorplan Design

Jiann-Horng LIN; Jing-Yang JOU; Iris Hui-Ru JIANG

Internet-Based Hierarchical Floorplan Design

Jiann-Horng LIN, Jing-Yang JOU, Iris Hui-Ru JIANG

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With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2414-2423

Publication Date: 1999/11/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Jiann-Horng LIN, Jing-Yang JOU, Iris Hui-Ru JIANG, "Internet-Based Hierarchical Floorplan Design" in IEICE TRANSACTIONS on Fundamentals, vol. E82-A, no. 11, pp. 2414-2423, November 1999, doi: .
Abstract: With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2414/_p

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@ARTICLE{e82-a_11_2414,
author={Jiann-Horng LIN, Jing-Yang JOU, Iris Hui-Ru JIANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Internet-Based Hierarchical Floorplan Design},
year={1999},
volume={E82-A},
number={11},
pages={2414-2423},
abstract={With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - Internet-Based Hierarchical Floorplan Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2414
EP - 2423
AU - Jiann-Horng LIN
AU - Jing-Yang JOU
AU - Iris Hui-Ru JIANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).
ER -