IEICE TRANSACTIONS on Fundamentals
Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier
Summary :
This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.2 pp.293-300
- Publication Date
- 1999/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
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Daisuke MIYAZAKI, Shoji KAWAHITO, Yoshiaki TADOKORO, "Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 293-300, February 1999, doi: .
Abstract: This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_293/_p
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@ARTICLE{e82-a_2_293,
author={Daisuke MIYAZAKI, Shoji KAWAHITO, Yoshiaki TADOKORO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier},
year={1999},
volume={E82-A},
number={2},
pages={293-300},
abstract={This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 293
EP - 300
AU - Daisuke MIYAZAKI
AU - Shoji KAWAHITO
AU - Yoshiaki TADOKORO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.
ER -
English
