IEICE TRANSACTIONS on Fundamentals
A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs
Summary :
This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.
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- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.3 pp.473-482
- Publication Date
- 1999/03/25
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- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
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Nozomu TOGAWA, Koji ARA, Masao YANAGISAWA, Tatsuo OHTSUKI, "A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 3, pp. 473-482, March 1999, doi: .
Abstract: This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_3_473/_p
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@ARTICLE{e82-a_3_473,
author={Nozomu TOGAWA, Koji ARA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs},
year={1999},
volume={E82-A},
number={3},
pages={473-482},
abstract={This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 473
EP - 482
AU - Nozomu TOGAWA
AU - Koji ARA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1999
AB - This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.
ER -
English
