High Speed Search and an Area Efficient Huffman Decoder

Seongmo PARK; Hanjin CHO; Jinjong CHA

High Speed Search and an Area Efficient Huffman Decoder

Seongmo PARK, Hanjin CHO, Jinjong CHA

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In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading 0'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 µm CMOS, 3.3V, technology.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.6 pp.1017-1020

Publication Date: 1999/06/25

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Type of Manuscript: Special Section LETTER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))

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Seongmo PARK, Hanjin CHO, Jinjong CHA, "High Speed Search and an Area Efficient Huffman Decoder" in IEICE TRANSACTIONS on Fundamentals, vol. E82-A, no. 6, pp. 1017-1020, June 1999, doi: .
Abstract: In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading 0'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 µm CMOS, 3.3V, technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_1017/_p

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@ARTICLE{e82-a_6_1017,
author={Seongmo PARK, Hanjin CHO, Jinjong CHA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High Speed Search and an Area Efficient Huffman Decoder},
year={1999},
volume={E82-A},
number={6},
pages={1017-1020},
abstract={In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading 0'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 µm CMOS, 3.3V, technology.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - High Speed Search and an Area Efficient Huffman Decoder
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1017
EP - 1020
AU - Seongmo PARK
AU - Hanjin CHO
AU - Jinjong CHA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading 0'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 µm CMOS, 3.3V, technology.
ER -