IEICE TRANSACTIONS on Fundamentals
A Scalable Pipelined Memory Architecture for Fast ATM Packet Switching
Summary :
This paper describes the design of a scalable pipelined memory buffer for a shared scalable buffer ATM switch. The memory architecture provides high speed and scalability, and eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. The architecture consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of a designed scalable memory is 4 ns. The designed memory is embedded in the prototype chip of a shared scalable buffer ATM switch with 4
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.9 pp.1937-1944
- Publication Date
- 1999/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Gab Joong JEONG, MoonKey LEE, "A Scalable Pipelined Memory Architecture for Fast ATM Packet Switching" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 9, pp. 1937-1944, September 1999, doi: .
Abstract: This paper describes the design of a scalable pipelined memory buffer for a shared scalable buffer ATM switch. The memory architecture provides high speed and scalability, and eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. The architecture consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of a designed scalable memory is 4 ns. The designed memory is embedded in the prototype chip of a shared scalable buffer ATM switch with 4
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_9_1937/_p
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@ARTICLE{e82-a_9_1937,
author={Gab Joong JEONG, MoonKey LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Scalable Pipelined Memory Architecture for Fast ATM Packet Switching},
year={1999},
volume={E82-A},
number={9},
pages={1937-1944},
abstract={This paper describes the design of a scalable pipelined memory buffer for a shared scalable buffer ATM switch. The memory architecture provides high speed and scalability, and eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. The architecture consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of a designed scalable memory is 4 ns. The designed memory is embedded in the prototype chip of a shared scalable buffer ATM switch with 4
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - A Scalable Pipelined Memory Architecture for Fast ATM Packet Switching
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1937
EP - 1944
AU - Gab Joong JEONG
AU - MoonKey LEE
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 1999
AB - This paper describes the design of a scalable pipelined memory buffer for a shared scalable buffer ATM switch. The memory architecture provides high speed and scalability, and eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. The architecture consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of a designed scalable memory is 4 ns. The designed memory is embedded in the prototype chip of a shared scalable buffer ATM switch with 4
ER -
English
