IEICE TRANSACTIONS on Fundamentals
Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure
Summary :
Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2520-2527
- Publication Date
- 2000/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
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Qiang ZHU, Yusuke MATSUNAGA, Shinji KIMURA, Katsumasa WATANABE, "Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2520-2527, December 2000, doi: .
Abstract: Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2520/_p
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@ARTICLE{e83-a_12_2520,
author={Qiang ZHU, Yusuke MATSUNAGA, Shinji KIMURA, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure},
year={2000},
volume={E83-A},
number={12},
pages={2520-2527},
abstract={Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2520
EP - 2527
AU - Qiang ZHU
AU - Yusuke MATSUNAGA
AU - Shinji KIMURA
AU - Katsumasa WATANABE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.
ER -
English
