High Level Analysis of Clock Regions in a C++ System Description
Summary :
Timing verification of digital synchronous designs is a complex process that is traditionally carried out deep in the design cycle, at the gate level. A method, embodied in a C++ based design system, is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, we are able to perform static and dynamic timing analysis of the clock regions.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.12 pp.2631-2632
- Publication Date
- 2000/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-level Synthesis
Authors
Keyword
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Luc RYNDERS, Patrick SCHAUMONT, Serge VERNALDE, Ivo BOLSENS, "High Level Analysis of Clock Regions in a C++ System Description" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2631-2632, December 2000, doi: .
Abstract: Timing verification of digital synchronous designs is a complex process that is traditionally carried out deep in the design cycle, at the gate level. A method, embodied in a C++ based design system, is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, we are able to perform static and dynamic timing analysis of the clock regions.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2631/_p
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@ARTICLE{e83-a_12_2631,
author={Luc RYNDERS, Patrick SCHAUMONT, Serge VERNALDE, Ivo BOLSENS, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High Level Analysis of Clock Regions in a C++ System Description},
year={2000},
volume={E83-A},
number={12},
pages={2631-2632},
abstract={Timing verification of digital synchronous designs is a complex process that is traditionally carried out deep in the design cycle, at the gate level. A method, embodied in a C++ based design system, is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, we are able to perform static and dynamic timing analysis of the clock regions.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - High Level Analysis of Clock Regions in a C++ System Description
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2631
EP - 2632
AU - Luc RYNDERS
AU - Patrick SCHAUMONT
AU - Serge VERNALDE
AU - Ivo BOLSENS
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - Timing verification of digital synchronous designs is a complex process that is traditionally carried out deep in the design cycle, at the gate level. A method, embodied in a C++ based design system, is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, we are able to perform static and dynamic timing analysis of the clock regions.
ER -
English
