Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using IDDQ
Summary :
Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal IDDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.5 pp.842-850
- Publication Date
- 2000/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Reliability Theory and Its Applications)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Masaru SANADA, Hiromu FUJIOKA, "Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using IDDQ" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 5, pp. 842-850, May 2000, doi: .
Abstract: Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal IDDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_5_842/_p
Copy
@ARTICLE{e83-a_5_842,
author={Masaru SANADA, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using IDDQ},
year={2000},
volume={E83-A},
number={5},
pages={842-850},
abstract={Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal IDDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using IDDQ
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 842
EP - 850
AU - Masaru SANADA
AU - Hiromu FUJIOKA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2000
AB - Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal IDDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.
ER -
English
