IEICE TRANSACTIONS on Fundamentals
Motion Estimation with Power Scalability and Its VHDL Model
Summary :
In MPEG standard, motion estimation (ME) is used to eliminate the temporal redundancy of video frames. This ME is the most time-consuming task in the encoding of video sequences and is also the one using the most power. Using low-bit images can save power of ME and a conventional architecture fixed to a certain bit width is used for low-bit motion estimator. It is known that there is a trade-off between power and image quality. ME may be used in various situations, and the relation between demands for power or image quality will depend on those circumstances. We therefore developed an architecture for a low-bit motion estimator with adjustable power consumption. In this architecture, we can select the bit width for the input image and adjust the amount of power for ME. To evaluate its effectiveness, we designed the motion estimator by VHDL and used the synthesis results to estimate the performance.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.8 pp.1608-1613
- Publication Date
- 2000/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Digital Signal Processing)
- Category
- Implementations of Signal Processing Systems
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Ayuko TAKAGI, Shogo MURAMATSU, Hitoshi KIYA, "Motion Estimation with Power Scalability and Its VHDL Model" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 8, pp. 1608-1613, August 2000, doi: .
Abstract: In MPEG standard, motion estimation (ME) is used to eliminate the temporal redundancy of video frames. This ME is the most time-consuming task in the encoding of video sequences and is also the one using the most power. Using low-bit images can save power of ME and a conventional architecture fixed to a certain bit width is used for low-bit motion estimator. It is known that there is a trade-off between power and image quality. ME may be used in various situations, and the relation between demands for power or image quality will depend on those circumstances. We therefore developed an architecture for a low-bit motion estimator with adjustable power consumption. In this architecture, we can select the bit width for the input image and adjust the amount of power for ME. To evaluate its effectiveness, we designed the motion estimator by VHDL and used the synthesis results to estimate the performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_8_1608/_p
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@ARTICLE{e83-a_8_1608,
author={Ayuko TAKAGI, Shogo MURAMATSU, Hitoshi KIYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Motion Estimation with Power Scalability and Its VHDL Model},
year={2000},
volume={E83-A},
number={8},
pages={1608-1613},
abstract={In MPEG standard, motion estimation (ME) is used to eliminate the temporal redundancy of video frames. This ME is the most time-consuming task in the encoding of video sequences and is also the one using the most power. Using low-bit images can save power of ME and a conventional architecture fixed to a certain bit width is used for low-bit motion estimator. It is known that there is a trade-off between power and image quality. ME may be used in various situations, and the relation between demands for power or image quality will depend on those circumstances. We therefore developed an architecture for a low-bit motion estimator with adjustable power consumption. In this architecture, we can select the bit width for the input image and adjust the amount of power for ME. To evaluate its effectiveness, we designed the motion estimator by VHDL and used the synthesis results to estimate the performance.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - Motion Estimation with Power Scalability and Its VHDL Model
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1608
EP - 1613
AU - Ayuko TAKAGI
AU - Shogo MURAMATSU
AU - Hitoshi KIYA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2000
AB - In MPEG standard, motion estimation (ME) is used to eliminate the temporal redundancy of video frames. This ME is the most time-consuming task in the encoding of video sequences and is also the one using the most power. Using low-bit images can save power of ME and a conventional architecture fixed to a certain bit width is used for low-bit motion estimator. It is known that there is a trade-off between power and image quality. ME may be used in various situations, and the relation between demands for power or image quality will depend on those circumstances. We therefore developed an architecture for a low-bit motion estimator with adjustable power consumption. In this architecture, we can select the bit width for the input image and adjust the amount of power for ME. To evaluate its effectiveness, we designed the motion estimator by VHDL and used the synthesis results to estimate the performance.
ER -
English
