IEICE TRANSACTIONS on Fundamentals
An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware
Summary :
This paper proposes a method for implementing a metric computation accelerator for fractal image compression using reconfigurable hardware. The most time-consuming part in the encoding of this compression is computation of metrics among image blocks. In our method, each processing element (PE) configured for an image block accelerates these computations by pipeline processing. Furthermore, by configuring the PE for a specific image block, we can reduce the number of adders, which are the main computing elements, by a half even in the worst case.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.1 pp.372-377
- Publication Date
- 2001/01/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- VLSI Design Technology and CAD
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Hidehisa NAGANO, Akihiro MATSUURA, Akira NAGOYA, "An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 1, pp. 372-377, January 2001, doi: .
Abstract: This paper proposes a method for implementing a metric computation accelerator for fractal image compression using reconfigurable hardware. The most time-consuming part in the encoding of this compression is computation of metrics among image blocks. In our method, each processing element (PE) configured for an image block accelerates these computations by pipeline processing. Furthermore, by configuring the PE for a specific image block, we can reduce the number of adders, which are the main computing elements, by a half even in the worst case.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_1_372/_p
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@ARTICLE{e84-a_1_372,
author={Hidehisa NAGANO, Akihiro MATSUURA, Akira NAGOYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware},
year={2001},
volume={E84-A},
number={1},
pages={372-377},
abstract={This paper proposes a method for implementing a metric computation accelerator for fractal image compression using reconfigurable hardware. The most time-consuming part in the encoding of this compression is computation of metrics among image blocks. In our method, each processing element (PE) configured for an image block accelerates these computations by pipeline processing. Furthermore, by configuring the PE for a specific image block, we can reduce the number of adders, which are the main computing elements, by a half even in the worst case.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 372
EP - 377
AU - Hidehisa NAGANO
AU - Akihiro MATSUURA
AU - Akira NAGOYA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2001
AB - This paper proposes a method for implementing a metric computation accelerator for fractal image compression using reconfigurable hardware. The most time-consuming part in the encoding of this compression is computation of metrics among image blocks. In our method, each processing element (PE) configured for an image block accelerates these computations by pipeline processing. Furthermore, by configuring the PE for a specific image block, we can reduce the number of adders, which are the main computing elements, by a half even in the worst case.
ER -
English
