IEICE TRANSACTIONS on Fundamentals
Code Optimization Technique for Indirect Addressing DSPs with Consideration in Local Computational Order and Memory Allocation
Summary :
Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.8 pp.1960-1968
- Publication Date
- 2001/08/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Digital Signal Processing)
- Category
- Implementations of Signal Processing Systems
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Nobuhiko SUGINO, Akinori NISHIHARA, "Code Optimization Technique for Indirect Addressing DSPs with Consideration in Local Computational Order and Memory Allocation" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 8, pp. 1960-1968, August 2001, doi: .
Abstract: Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_8_1960/_p
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@ARTICLE{e84-a_8_1960,
author={Nobuhiko SUGINO, Akinori NISHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Code Optimization Technique for Indirect Addressing DSPs with Consideration in Local Computational Order and Memory Allocation},
year={2001},
volume={E84-A},
number={8},
pages={1960-1968},
abstract={Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Code Optimization Technique for Indirect Addressing DSPs with Consideration in Local Computational Order and Memory Allocation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1960
EP - 1968
AU - Nobuhiko SUGINO
AU - Akinori NISHIHARA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2001
AB - Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.
ER -
English
