IEICE TRANSACTIONS on Fundamentals
Modular Synthesis of Timed Circuits Using Partial Order Reduction
Summary :
This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2684-2692
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
Authors
Keyword
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Tomohiro YONEDA, Eric MERCER, Chris MYERS, "Modular Synthesis of Timed Circuits Using Partial Order Reduction" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2684-2692, December 2002, doi: .
Abstract: This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2684/_p
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@ARTICLE{e85-a_12_2684,
author={Tomohiro YONEDA, Eric MERCER, Chris MYERS, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modular Synthesis of Timed Circuits Using Partial Order Reduction},
year={2002},
volume={E85-A},
number={12},
pages={2684-2692},
abstract={This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Modular Synthesis of Timed Circuits Using Partial Order Reduction
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2684
EP - 2692
AU - Tomohiro YONEDA
AU - Eric MERCER
AU - Chris MYERS
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible.
ER -
English
