IEICE TRANSACTIONS on Fundamentals
SP2: A Very Large-Scale Event Driven Logic Simulation Hardware
Summary :
This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2737-2745
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Simulation
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Keyword
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Hirofumi HAMAMURA, Hiroaki KOMATSU, "SP2: A Very Large-Scale Event Driven Logic Simulation Hardware" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2737-2745, December 2002, doi: .
Abstract: This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2737/_p
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@ARTICLE{e85-a_12_2737,
author={Hirofumi HAMAMURA, Hiroaki KOMATSU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={SP2: A Very Large-Scale Event Driven Logic Simulation Hardware},
year={2002},
volume={E85-A},
number={12},
pages={2737-2745},
abstract={This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - SP2: A Very Large-Scale Event Driven Logic Simulation Hardware
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2737
EP - 2745
AU - Hirofumi HAMAMURA
AU - Hiroaki KOMATSU
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.
ER -
English
