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As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay of a net comes to have a considerable effect on the clock period. Therefore, it is required to minimize signal delays in digital VLSIs. There are a number of ways to evaluate a signal delay of a net, such as cost, radius, and Elmore's delay. Delays of those models can be computed in linear time. Elmore's delay model takes both capacitance and resistance into account and it is often regarded as a reasonable model. So, it is important to investigate the properties of this model. In this paper, we investigate the properties of the model and construct a heuristic algorithm based on these properties for computing a wiring of a net to minimize the interconnection delay. We show the effectiveness of our proposed algorithm by comparing ERT algorithm which is proposed in [2] for minimizing the maximum Elmore's delay of a sink. Our proposed algorithm decreases the average of the maximum Elmore's delay by 10-20% for ERT algorithm. We also compare our algorithm with an *O*(*n*^{4}) algorithm proposed in [15] and confirm the effectiveness of our algorithm though its time complexity is *O*(*n*^{3}).

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2764-2774

- Publication Date
- 2002/12/01

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category
- Timing Analysis

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Satoshi TAYU, Mineo KANEKO, "Characterization and Computation of Steiner Routing Based on Elmore's Delay Model" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2764-2774, December 2002, doi: .

Abstract: As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay of a net comes to have a considerable effect on the clock period. Therefore, it is required to minimize signal delays in digital VLSIs. There are a number of ways to evaluate a signal delay of a net, such as cost, radius, and Elmore's delay. Delays of those models can be computed in linear time. Elmore's delay model takes both capacitance and resistance into account and it is often regarded as a reasonable model. So, it is important to investigate the properties of this model. In this paper, we investigate the properties of the model and construct a heuristic algorithm based on these properties for computing a wiring of a net to minimize the interconnection delay. We show the effectiveness of our proposed algorithm by comparing ERT algorithm which is proposed in [2] for minimizing the maximum Elmore's delay of a sink. Our proposed algorithm decreases the average of the maximum Elmore's delay by 10-20% for ERT algorithm. We also compare our algorithm with an *O*(*n*^{4}) algorithm proposed in [15] and confirm the effectiveness of our algorithm though its time complexity is *O*(*n*^{3}).

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2764/_p

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@ARTICLE{e85-a_12_2764,

author={Satoshi TAYU, Mineo KANEKO, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Characterization and Computation of Steiner Routing Based on Elmore's Delay Model},

year={2002},

volume={E85-A},

number={12},

pages={2764-2774},

abstract={As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay of a net comes to have a considerable effect on the clock period. Therefore, it is required to minimize signal delays in digital VLSIs. There are a number of ways to evaluate a signal delay of a net, such as cost, radius, and Elmore's delay. Delays of those models can be computed in linear time. Elmore's delay model takes both capacitance and resistance into account and it is often regarded as a reasonable model. So, it is important to investigate the properties of this model. In this paper, we investigate the properties of the model and construct a heuristic algorithm based on these properties for computing a wiring of a net to minimize the interconnection delay. We show the effectiveness of our proposed algorithm by comparing ERT algorithm which is proposed in [2] for minimizing the maximum Elmore's delay of a sink. Our proposed algorithm decreases the average of the maximum Elmore's delay by 10-20% for ERT algorithm. We also compare our algorithm with an *O*(*n*^{4}) algorithm proposed in [15] and confirm the effectiveness of our algorithm though its time complexity is *O*(*n*^{3}).},

keywords={},

doi={},

ISSN={},

month={December},}

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TY - JOUR

TI - Characterization and Computation of Steiner Routing Based on Elmore's Delay Model

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2764

EP - 2774

AU - Satoshi TAYU

AU - Mineo KANEKO

PY - 2002

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E85-A

IS - 12

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - December 2002

AB - As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay of a net comes to have a considerable effect on the clock period. Therefore, it is required to minimize signal delays in digital VLSIs. There are a number of ways to evaluate a signal delay of a net, such as cost, radius, and Elmore's delay. Delays of those models can be computed in linear time. Elmore's delay model takes both capacitance and resistance into account and it is often regarded as a reasonable model. So, it is important to investigate the properties of this model. In this paper, we investigate the properties of the model and construct a heuristic algorithm based on these properties for computing a wiring of a net to minimize the interconnection delay. We show the effectiveness of our proposed algorithm by comparing ERT algorithm which is proposed in [2] for minimizing the maximum Elmore's delay of a sink. Our proposed algorithm decreases the average of the maximum Elmore's delay by 10-20% for ERT algorithm. We also compare our algorithm with an *O*(*n*^{4}) algorithm proposed in [15] and confirm the effectiveness of our algorithm though its time complexity is *O*(*n*^{3}).

ER -