Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture

Jun Kyoung KIM; Ho Young KIM; Tag Gon KIM

Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture

Jun Kyoung KIM, Ho Young KIM, Tag Gon KIM

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This paper proposes a retargetable framework for rapid evaluation of processor architecture, which represents abstraction levels of architecture in a hierarchical manner. The basis for such framework is a hierarchical architecture description language, called XR², which describes architecture at three abstraction levels: instruction set architecture, pipeline architecture and micro-architecture. In addition, a token-level computational model for fast pipeline simulation is proposed, which considers the minimal information required for the given performance measurement of the pipeline. Experimental result shows that token-level simulation is faster than the traditional cycle-accurate one by 50% to 80% in pipeline architecture evaluation.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3089-3098

Publication Date: 2003/12/01

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Simulation Accelerator

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Jun Kyoung KIM, Ho Young KIM, Tag Gon KIM, "Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 3089-3098, December 2003, doi: .
Abstract: This paper proposes a retargetable framework for rapid evaluation of processor architecture, which represents abstraction levels of architecture in a hierarchical manner. The basis for such framework is a hierarchical architecture description language, called XR², which describes architecture at three abstraction levels: instruction set architecture, pipeline architecture and micro-architecture. In addition, a token-level computational model for fast pipeline simulation is proposed, which considers the minimal information required for the given performance measurement of the pipeline. Experimental result shows that token-level simulation is faster than the traditional cycle-accurate one by 50% to 80% in pipeline architecture evaluation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3089/_p

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@ARTICLE{e86-a_12_3089,
author={Jun Kyoung KIM, Ho Young KIM, Tag Gon KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture},
year={2003},
volume={E86-A},
number={12},
pages={3089-3098},
abstract={This paper proposes a retargetable framework for rapid evaluation of processor architecture, which represents abstraction levels of architecture in a hierarchical manner. The basis for such framework is a hierarchical architecture description language, called XR², which describes architecture at three abstraction levels: instruction set architecture, pipeline architecture and micro-architecture. In addition, a token-level computational model for fast pipeline simulation is proposed, which considers the minimal information required for the given performance measurement of the pipeline. Experimental result shows that token-level simulation is faster than the traditional cycle-accurate one by 50% to 80% in pipeline architecture evaluation.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3089
EP - 3098
AU - Jun Kyoung KIM
AU - Ho Young KIM
AU - Tag Gon KIM
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - This paper proposes a retargetable framework for rapid evaluation of processor architecture, which represents abstraction levels of architecture in a hierarchical manner. The basis for such framework is a hierarchical architecture description language, called XR², which describes architecture at three abstraction levels: instruction set architecture, pipeline architecture and micro-architecture. In addition, a token-level computational model for fast pipeline simulation is proposed, which considers the minimal information required for the given performance measurement of the pipeline. Experimental result shows that token-level simulation is faster than the traditional cycle-accurate one by 50% to 80% in pipeline architecture evaluation.
ER -