Design of High-Performance Charge-Pump Circuit for PLL Applications
Summary :
This work proposed a high-performance charge-pump circuit for phase-locked-loop (PLL) applications. The proposed charge-pump circuit is composed of a pair of wide-swing current mirror and symmetric pump circuits which can provide wide output range and have no jump phenomenon. The proposed charge-pump circuit has been designed and simulated by using the TSMC 0.35 µm 1P4M CMOS technology. Simulation results show the feasibility of proposed structure for low-voltage high-frequency applications.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3211-3213
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Analog Design
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Keyword
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Chun-Lung HSU, Wu-Hung LU, "Design of High-Performance Charge-Pump Circuit for PLL Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 3211-3213, December 2003, doi: .
Abstract: This work proposed a high-performance charge-pump circuit for phase-locked-loop (PLL) applications. The proposed charge-pump circuit is composed of a pair of wide-swing current mirror and symmetric pump circuits which can provide wide output range and have no jump phenomenon. The proposed charge-pump circuit has been designed and simulated by using the TSMC 0.35 µm 1P4M CMOS technology. Simulation results show the feasibility of proposed structure for low-voltage high-frequency applications.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3211/_p
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@ARTICLE{e86-a_12_3211,
author={Chun-Lung HSU, Wu-Hung LU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of High-Performance Charge-Pump Circuit for PLL Applications},
year={2003},
volume={E86-A},
number={12},
pages={3211-3213},
abstract={This work proposed a high-performance charge-pump circuit for phase-locked-loop (PLL) applications. The proposed charge-pump circuit is composed of a pair of wide-swing current mirror and symmetric pump circuits which can provide wide output range and have no jump phenomenon. The proposed charge-pump circuit has been designed and simulated by using the TSMC 0.35 µm 1P4M CMOS technology. Simulation results show the feasibility of proposed structure for low-voltage high-frequency applications.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Design of High-Performance Charge-Pump Circuit for PLL Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3211
EP - 3213
AU - Chun-Lung HSU
AU - Wu-Hung LU
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - This work proposed a high-performance charge-pump circuit for phase-locked-loop (PLL) applications. The proposed charge-pump circuit is composed of a pair of wide-swing current mirror and symmetric pump circuits which can provide wide output range and have no jump phenomenon. The proposed charge-pump circuit has been designed and simulated by using the TSMC 0.35 µm 1P4M CMOS technology. Simulation results show the feasibility of proposed structure for low-voltage high-frequency applications.
ER -
English
