IEICE TRANSACTIONS on Fundamentals
Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser
Summary :
This paper presents the implementation of sfl2vl, a new free tool for SFL to Verilog conversion. Also this paper will discuss the performance of the conversion and the logic simulation of the sfl2vl+Icarus Verilog (free-ware compiler) versus PARTHENON with some MPU designs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3225-3229
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Design Methodology
Authors
Keyword
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Naohiko SHIMIZU, "Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 3225-3229, December 2003, doi: .
Abstract: This paper presents the implementation of sfl2vl, a new free tool for SFL to Verilog conversion. Also this paper will discuss the performance of the conversion and the logic simulation of the sfl2vl+Icarus Verilog (free-ware compiler) versus PARTHENON with some MPU designs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3225/_p
Copy
@ARTICLE{e86-a_12_3225,
author={Naohiko SHIMIZU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser},
year={2003},
volume={E86-A},
number={12},
pages={3225-3229},
abstract={This paper presents the implementation of sfl2vl, a new free tool for SFL to Verilog conversion. Also this paper will discuss the performance of the conversion and the logic simulation of the sfl2vl+Icarus Verilog (free-ware compiler) versus PARTHENON with some MPU designs.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3225
EP - 3229
AU - Naohiko SHIMIZU
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - This paper presents the implementation of sfl2vl, a new free tool for SFL to Verilog conversion. Also this paper will discuss the performance of the conversion and the logic simulation of the sfl2vl+Icarus Verilog (free-ware compiler) versus PARTHENON with some MPU designs.
ER -
English
