IEICE TRANSACTIONS on Fundamentals
An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design
Summary :
This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3297-3302
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- VLSI Design Technology and CAD
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Yeong-Geol KIM, Tag-Gon KIM, "An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 3297-3302, December 2003, doi: .
Abstract: This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3297/_p
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@ARTICLE{e86-a_12_3297,
author={Yeong-Geol KIM, Tag-Gon KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design},
year={2003},
volume={E86-A},
number={12},
pages={3297-3302},
abstract={This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3297
EP - 3302
AU - Yeong-Geol KIM
AU - Tag-Gon KIM
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.
ER -
English
