A Hierarchical Cost Estimation Technique for High Level Synthesis
Summary :
The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.2 pp.444-461
- Publication Date
- 2003/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Mahmoud MERIBOUT, Masato MOTOMURA, "A Hierarchical Cost Estimation Technique for High Level Synthesis" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 2, pp. 444-461, February 2003, doi: .
Abstract: The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_2_444/_p
Copy
@ARTICLE{e86-a_2_444,
author={Mahmoud MERIBOUT, Masato MOTOMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hierarchical Cost Estimation Technique for High Level Synthesis},
year={2003},
volume={E86-A},
number={2},
pages={444-461},
abstract={The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A Hierarchical Cost Estimation Technique for High Level Synthesis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 444
EP - 461
AU - Mahmoud MERIBOUT
AU - Masato MOTOMURA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2003
AB - The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.
ER -
English
