IEICE TRANSACTIONS on Fundamentals
Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits
Summary :
The interconnection problem of binary circuits becomes seriously as the exponential growth of the circuits complexity has been driven by a combination of down scaling of the device size and up scaling of the chip size. Motivated by the problem, there is much research of circuits based on multiple-valued logic. On the other hand, caused by the signal propagation delay, there exist hazards in binary logic circuits. To analyze hazards in binary logic circuits, many multiple-valued logics have been proposed, and studied on their mathematical properties. The paper will discuss on a multiple-valued logic which is suitable for treating static hazards in multiple-valued logic circuits. Then, the paper will show that the prime implicants expressions of r-valued logic functions realize static hazards free r-valued logic circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.6 pp.1525-1534
- Publication Date
- 2003/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Noboru TAKAGI, Kyoichi NAKASHIMA, "Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 6, pp. 1525-1534, June 2003, doi: .
Abstract: The interconnection problem of binary circuits becomes seriously as the exponential growth of the circuits complexity has been driven by a combination of down scaling of the device size and up scaling of the chip size. Motivated by the problem, there is much research of circuits based on multiple-valued logic. On the other hand, caused by the signal propagation delay, there exist hazards in binary logic circuits. To analyze hazards in binary logic circuits, many multiple-valued logics have been proposed, and studied on their mathematical properties. The paper will discuss on a multiple-valued logic which is suitable for treating static hazards in multiple-valued logic circuits. Then, the paper will show that the prime implicants expressions of r-valued logic functions realize static hazards free r-valued logic circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_6_1525/_p
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@ARTICLE{e86-a_6_1525,
author={Noboru TAKAGI, Kyoichi NAKASHIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits},
year={2003},
volume={E86-A},
number={6},
pages={1525-1534},
abstract={The interconnection problem of binary circuits becomes seriously as the exponential growth of the circuits complexity has been driven by a combination of down scaling of the device size and up scaling of the chip size. Motivated by the problem, there is much research of circuits based on multiple-valued logic. On the other hand, caused by the signal propagation delay, there exist hazards in binary logic circuits. To analyze hazards in binary logic circuits, many multiple-valued logics have been proposed, and studied on their mathematical properties. The paper will discuss on a multiple-valued logic which is suitable for treating static hazards in multiple-valued logic circuits. Then, the paper will show that the prime implicants expressions of r-valued logic functions realize static hazards free r-valued logic circuits.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1525
EP - 1534
AU - Noboru TAKAGI
AU - Kyoichi NAKASHIMA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2003
AB - The interconnection problem of binary circuits becomes seriously as the exponential growth of the circuits complexity has been driven by a combination of down scaling of the device size and up scaling of the chip size. Motivated by the problem, there is much research of circuits based on multiple-valued logic. On the other hand, caused by the signal propagation delay, there exist hazards in binary logic circuits. To analyze hazards in binary logic circuits, many multiple-valued logics have been proposed, and studied on their mathematical properties. The paper will discuss on a multiple-valued logic which is suitable for treating static hazards in multiple-valued logic circuits. Then, the paper will show that the prime implicants expressions of r-valued logic functions realize static hazards free r-valued logic circuits.
ER -
English
