IEICE TRANSACTIONS on Fundamentals
FPGA-Based Reconfigurable Adaptive FEC
Summary :
In this paper, we propose a reconfigurable adaptive FEC system. In adaptive FEC schemes, the error correction capability t is changed dynamically according to the communication channel condition. If a particular error correction capability t is given, we can implement an FEC decoder which is optimal for t by taking the number of operations into consideration. Thus, reconfiguring the optimal FEC decoder dynamically for each error correction capability allows us to maximize the throughput of each decoder within a limited hardware resource. Based on this concept, our reconfigurable adaptive FEC system can reduce the packet dropping rate more efficiently than conventional fixed hardware systems. We can improve data transmission throughput for a reliable transport protocol. Practical simulation results are also shown.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3036-3046
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- System Level Design
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Kazunori SHIMIZU, Jumpei UCHIDA, Yuichiro MIYAOKA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, "FPGA-Based Reconfigurable Adaptive FEC" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3036-3046, December 2004, doi: .
Abstract: In this paper, we propose a reconfigurable adaptive FEC system. In adaptive FEC schemes, the error correction capability t is changed dynamically according to the communication channel condition. If a particular error correction capability t is given, we can implement an FEC decoder which is optimal for t by taking the number of operations into consideration. Thus, reconfiguring the optimal FEC decoder dynamically for each error correction capability allows us to maximize the throughput of each decoder within a limited hardware resource. Based on this concept, our reconfigurable adaptive FEC system can reduce the packet dropping rate more efficiently than conventional fixed hardware systems. We can improve data transmission throughput for a reliable transport protocol. Practical simulation results are also shown.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3036/_p
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@ARTICLE{e87-a_12_3036,
author={Kazunori SHIMIZU, Jumpei UCHIDA, Yuichiro MIYAOKA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={FPGA-Based Reconfigurable Adaptive FEC},
year={2004},
volume={E87-A},
number={12},
pages={3036-3046},
abstract={In this paper, we propose a reconfigurable adaptive FEC system. In adaptive FEC schemes, the error correction capability t is changed dynamically according to the communication channel condition. If a particular error correction capability t is given, we can implement an FEC decoder which is optimal for t by taking the number of operations into consideration. Thus, reconfiguring the optimal FEC decoder dynamically for each error correction capability allows us to maximize the throughput of each decoder within a limited hardware resource. Based on this concept, our reconfigurable adaptive FEC system can reduce the packet dropping rate more efficiently than conventional fixed hardware systems. We can improve data transmission throughput for a reliable transport protocol. Practical simulation results are also shown.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - FPGA-Based Reconfigurable Adaptive FEC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3036
EP - 3046
AU - Kazunori SHIMIZU
AU - Jumpei UCHIDA
AU - Yuichiro MIYAOKA
AU - Nozomu TOGAWA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - In this paper, we propose a reconfigurable adaptive FEC system. In adaptive FEC schemes, the error correction capability t is changed dynamically according to the communication channel condition. If a particular error correction capability t is given, we can implement an FEC decoder which is optimal for t by taking the number of operations into consideration. Thus, reconfiguring the optimal FEC decoder dynamically for each error correction capability allows us to maximize the throughput of each decoder within a limited hardware resource. Based on this concept, our reconfigurable adaptive FEC system can reduce the packet dropping rate more efficiently than conventional fixed hardware systems. We can improve data transmission throughput for a reliable transport protocol. Practical simulation results are also shown.
ER -
English
