IEICE TRANSACTIONS on Fundamentals
SoC Architecture Synthesis Methodology Based on High-Level IPs
Summary :
We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3057-3067
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- System Level Design
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Michiaki MURAOKA, Hiroaki NISHI, Rafael K. MORIZAWA, Hideaki YOKOTA, Yoichi ONISHI, "SoC Architecture Synthesis Methodology Based on High-Level IPs" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3057-3067, December 2004, doi: .
Abstract: We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3057/_p
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@ARTICLE{e87-a_12_3057,
author={Michiaki MURAOKA, Hiroaki NISHI, Rafael K. MORIZAWA, Hideaki YOKOTA, Yoichi ONISHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={SoC Architecture Synthesis Methodology Based on High-Level IPs},
year={2004},
volume={E87-A},
number={12},
pages={3057-3067},
abstract={We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - SoC Architecture Synthesis Methodology Based on High-Level IPs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3057
EP - 3067
AU - Michiaki MURAOKA
AU - Hiroaki NISHI
AU - Rafael K. MORIZAWA
AU - Hideaki YOKOTA
AU - Yoichi ONISHI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.
ER -
English
