IEICE TRANSACTIONS on Fundamentals
A Novel Digitally-Controlled Varactor for Portable Delay Cell Design
Summary :
In this paper, a novel digitally-controlled varactor (DCV) for portable delay cell design is presented. The proposed varactor uses the gate capacitance differences of NAND/NOR gates under different digital control inputs to build up a digitally-controlled varactor. Then the proposed varactor is applied to design a high resolution delay cell and to achieve a fine delay resolution. Different types of NAND/NOR gates (2-input or 3-input) for DCV design are also investigated in this paper. The proposed DCV can be implemented with standard cells, thus it can be easily ported to different processes in a short time. A test chip fabricated on a standard 0.35 µm CMOS 2P4M process proves that the proposed delay cell has a fine delay resolution about 1.55 ps. As a result, the proposed DCV exhibits finer resolution, better linearity, and better portability than traditional delay elements, and is very suitable for portable delay cell design.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3324-3326
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Design
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Pao-Lung CHEN, Ching-Che CHUNG, Chen-Yi LEE, "A Novel Digitally-Controlled Varactor for Portable Delay Cell Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3324-3326, December 2004, doi: .
Abstract: In this paper, a novel digitally-controlled varactor (DCV) for portable delay cell design is presented. The proposed varactor uses the gate capacitance differences of NAND/NOR gates under different digital control inputs to build up a digitally-controlled varactor. Then the proposed varactor is applied to design a high resolution delay cell and to achieve a fine delay resolution. Different types of NAND/NOR gates (2-input or 3-input) for DCV design are also investigated in this paper. The proposed DCV can be implemented with standard cells, thus it can be easily ported to different processes in a short time. A test chip fabricated on a standard 0.35 µm CMOS 2P4M process proves that the proposed delay cell has a fine delay resolution about 1.55 ps. As a result, the proposed DCV exhibits finer resolution, better linearity, and better portability than traditional delay elements, and is very suitable for portable delay cell design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3324/_p
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@ARTICLE{e87-a_12_3324,
author={Pao-Lung CHEN, Ching-Che CHUNG, Chen-Yi LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Novel Digitally-Controlled Varactor for Portable Delay Cell Design},
year={2004},
volume={E87-A},
number={12},
pages={3324-3326},
abstract={In this paper, a novel digitally-controlled varactor (DCV) for portable delay cell design is presented. The proposed varactor uses the gate capacitance differences of NAND/NOR gates under different digital control inputs to build up a digitally-controlled varactor. Then the proposed varactor is applied to design a high resolution delay cell and to achieve a fine delay resolution. Different types of NAND/NOR gates (2-input or 3-input) for DCV design are also investigated in this paper. The proposed DCV can be implemented with standard cells, thus it can be easily ported to different processes in a short time. A test chip fabricated on a standard 0.35 µm CMOS 2P4M process proves that the proposed delay cell has a fine delay resolution about 1.55 ps. As a result, the proposed DCV exhibits finer resolution, better linearity, and better portability than traditional delay elements, and is very suitable for portable delay cell design.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Novel Digitally-Controlled Varactor for Portable Delay Cell Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3324
EP - 3326
AU - Pao-Lung CHEN
AU - Ching-Che CHUNG
AU - Chen-Yi LEE
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - In this paper, a novel digitally-controlled varactor (DCV) for portable delay cell design is presented. The proposed varactor uses the gate capacitance differences of NAND/NOR gates under different digital control inputs to build up a digitally-controlled varactor. Then the proposed varactor is applied to design a high resolution delay cell and to achieve a fine delay resolution. Different types of NAND/NOR gates (2-input or 3-input) for DCV design are also investigated in this paper. The proposed DCV can be implemented with standard cells, thus it can be easily ported to different processes in a short time. A test chip fabricated on a standard 0.35 µm CMOS 2P4M process proves that the proposed delay cell has a fine delay resolution about 1.55 ps. As a result, the proposed DCV exhibits finer resolution, better linearity, and better portability than traditional delay elements, and is very suitable for portable delay cell design.
ER -
English
