IEICE TRANSACTIONS on Fundamentals
A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths
Summary :
This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.
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- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.4 pp.830-836
- Publication Date
- 2004/04/01
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- Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
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Yuichiro MIYAOKA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, "A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 4, pp. 830-836, April 2004, doi: .
Abstract: This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_4_830/_p
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@ARTICLE{e87-a_4_830,
author={Yuichiro MIYAOKA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths},
year={2004},
volume={E87-A},
number={4},
pages={830-836},
abstract={This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 830
EP - 836
AU - Yuichiro MIYAOKA
AU - Nozomu TOGAWA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2004
AB - This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.
ER -
English
