Low-Power Real-Time Video CODEC for 16-Channel DVR Security System

Seonyoung LEE; Kyeongsoon CHO

Low-Power Real-Time Video CODEC for 16-Channel DVR Security System

Seonyoung LEE, Kyeongsoon CHO

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This paper presents the architecture and design of the video CODEC circuit that can compress and reconstruct 4:2:2 color VGA video images in real time. Our circuit is based on two-dimensional DWT and inter-frame compression technique. For low-power real-time operation, we modified the traditional Mallat's sub-band coding method to reduce the amount of computation and memory access required in two-dimensional DWT. We also incorporated inter-frame compression technique into our CODEC circuit to enhance the compression capability. To avoid an intensive computation required in motion detection, we encoded only the macro blocks in the current frame which are different from those in the same location of the previous frame to exploit the fact that the background image does not change much in DVR system. We fabricated the CODEC chip using 0.35 µm 3.3 V CMOS standard cell process and applied it to the 16-channel DVR security system.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.6 pp.1290-1296

Publication Date: 2004/06/01

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Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))

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Seonyoung LEE, Kyeongsoon CHO, "Low-Power Real-Time Video CODEC for 16-Channel DVR Security System" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 6, pp. 1290-1296, June 2004, doi: .
Abstract: This paper presents the architecture and design of the video CODEC circuit that can compress and reconstruct 4:2:2 color VGA video images in real time. Our circuit is based on two-dimensional DWT and inter-frame compression technique. For low-power real-time operation, we modified the traditional Mallat's sub-band coding method to reduce the amount of computation and memory access required in two-dimensional DWT. We also incorporated inter-frame compression technique into our CODEC circuit to enhance the compression capability. To avoid an intensive computation required in motion detection, we encoded only the macro blocks in the current frame which are different from those in the same location of the previous frame to exploit the fact that the background image does not change much in DVR system. We fabricated the CODEC chip using 0.35 µm 3.3 V CMOS standard cell process and applied it to the 16-channel DVR security system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_6_1290/_p

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@ARTICLE{e87-a_6_1290,
author={Seonyoung LEE, Kyeongsoon CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low-Power Real-Time Video CODEC for 16-Channel DVR Security System},
year={2004},
volume={E87-A},
number={6},
pages={1290-1296},
abstract={This paper presents the architecture and design of the video CODEC circuit that can compress and reconstruct 4:2:2 color VGA video images in real time. Our circuit is based on two-dimensional DWT and inter-frame compression technique. For low-power real-time operation, we modified the traditional Mallat's sub-band coding method to reduce the amount of computation and memory access required in two-dimensional DWT. We also incorporated inter-frame compression technique into our CODEC circuit to enhance the compression capability. To avoid an intensive computation required in motion detection, we encoded only the macro blocks in the current frame which are different from those in the same location of the previous frame to exploit the fact that the background image does not change much in DVR system. We fabricated the CODEC chip using 0.35 µm 3.3 V CMOS standard cell process and applied it to the 16-channel DVR security system.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - Low-Power Real-Time Video CODEC for 16-Channel DVR Security System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1290
EP - 1296
AU - Seonyoung LEE
AU - Kyeongsoon CHO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2004
AB - This paper presents the architecture and design of the video CODEC circuit that can compress and reconstruct 4:2:2 color VGA video images in real time. Our circuit is based on two-dimensional DWT and inter-frame compression technique. For low-power real-time operation, we modified the traditional Mallat's sub-band coding method to reduce the amount of computation and memory access required in two-dimensional DWT. We also incorporated inter-frame compression technique into our CODEC circuit to enhance the compression capability. To avoid an intensive computation required in motion detection, we encoded only the macro blocks in the current frame which are different from those in the same location of the previous frame to exploit the fact that the background image does not change much in DVR system. We fabricated the CODEC chip using 0.35 µm 3.3 V CMOS standard cell process and applied it to the 16-channel DVR security system.
ER -