Digital/Analog Hybrid Implementation of Cardinal Spline Interpolation

Masaru KAMADA; Mitsuhiro MATSUO

Digital/Analog Hybrid Implementation of Cardinal Spline Interpolation

Masaru KAMADA, Mitsuhiro MATSUO

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A digital/analog hybrid system is presented which implements the cardinal polynomial spline interpolation of arbitrary degree. Based on the fact that the (m-1)st derivative of a spline of degree m-1 is a staircase function, this system generates a cardinal spline of degree m-1 by m-1 cascaded integrators with a staircase function input. A given sequence of sampled values are transformed by a digital filter into coefficients for the B-spline representation of the spline interpolating the sampled values. The values of its (m-1)st derivative with respect to time are computed by the recurrence formula interpreting differentiation of the spline as difference of the coefficients. Then a digital-to-analog converter generates a staircase function representing the (m-1)st derivative, which is integrated by a cascade of m-1 analog integrators to make the expected spline. In order to cope with the offset errors involved in the integrators, a dynamical sampled-data control is attached. An analog-to-digital converter is employed to sample the output of the cascaded integrators. Target state of the cascaded integrators at each sampling instance is computed from the coefficients for the B-spline representation. The state error between the target and the estimated is compensated by feeding back a weighted sum of the state error to the staircase input.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.9 pp.2412-2419

Publication Date: 2004/09/01

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Type of Manuscript: PAPER

Category: Digital Signal Processing

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Masaru KAMADA, Mitsuhiro MATSUO, "Digital/Analog Hybrid Implementation of Cardinal Spline Interpolation" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 9, pp. 2412-2419, September 2004, doi: .
Abstract: A digital/analog hybrid system is presented which implements the cardinal polynomial spline interpolation of arbitrary degree. Based on the fact that the (m-1)st derivative of a spline of degree m-1 is a staircase function, this system generates a cardinal spline of degree m-1 by m-1 cascaded integrators with a staircase function input. A given sequence of sampled values are transformed by a digital filter into coefficients for the B-spline representation of the spline interpolating the sampled values. The values of its (m-1)st derivative with respect to time are computed by the recurrence formula interpreting differentiation of the spline as difference of the coefficients. Then a digital-to-analog converter generates a staircase function representing the (m-1)st derivative, which is integrated by a cascade of m-1 analog integrators to make the expected spline. In order to cope with the offset errors involved in the integrators, a dynamical sampled-data control is attached. An analog-to-digital converter is employed to sample the output of the cascaded integrators. Target state of the cascaded integrators at each sampling instance is computed from the coefficients for the B-spline representation. The state error between the target and the estimated is compensated by feeding back a weighted sum of the state error to the staircase input.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_9_2412/_p

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@ARTICLE{e87-a_9_2412,
author={Masaru KAMADA, Mitsuhiro MATSUO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Digital/Analog Hybrid Implementation of Cardinal Spline Interpolation},
year={2004},
volume={E87-A},
number={9},
pages={2412-2419},
abstract={A digital/analog hybrid system is presented which implements the cardinal polynomial spline interpolation of arbitrary degree. Based on the fact that the (m-1)st derivative of a spline of degree m-1 is a staircase function, this system generates a cardinal spline of degree m-1 by m-1 cascaded integrators with a staircase function input. A given sequence of sampled values are transformed by a digital filter into coefficients for the B-spline representation of the spline interpolating the sampled values. The values of its (m-1)st derivative with respect to time are computed by the recurrence formula interpreting differentiation of the spline as difference of the coefficients. Then a digital-to-analog converter generates a staircase function representing the (m-1)st derivative, which is integrated by a cascade of m-1 analog integrators to make the expected spline. In order to cope with the offset errors involved in the integrators, a dynamical sampled-data control is attached. An analog-to-digital converter is employed to sample the output of the cascaded integrators. Target state of the cascaded integrators at each sampling instance is computed from the coefficients for the B-spline representation. The state error between the target and the estimated is compensated by feeding back a weighted sum of the state error to the staircase input.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Digital/Analog Hybrid Implementation of Cardinal Spline Interpolation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2412
EP - 2419
AU - Masaru KAMADA
AU - Mitsuhiro MATSUO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2004
AB - A digital/analog hybrid system is presented which implements the cardinal polynomial spline interpolation of arbitrary degree. Based on the fact that the (m-1)st derivative of a spline of degree m-1 is a staircase function, this system generates a cardinal spline of degree m-1 by m-1 cascaded integrators with a staircase function input. A given sequence of sampled values are transformed by a digital filter into coefficients for the B-spline representation of the spline interpolating the sampled values. The values of its (m-1)st derivative with respect to time are computed by the recurrence formula interpreting differentiation of the spline as difference of the coefficients. Then a digital-to-analog converter generates a staircase function representing the (m-1)st derivative, which is integrated by a cascade of m-1 analog integrators to make the expected spline. In order to cope with the offset errors involved in the integrators, a dynamical sampled-data control is attached. An analog-to-digital converter is employed to sample the output of the cascaded integrators. Target state of the cascaded integrators at each sampling instance is computed from the coefficients for the B-spline representation. The state error between the target and the estimated is compensated by feeding back a weighted sum of the state error to the staircase input.
ER -