IEICE TRANSACTIONS on Fundamentals
Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design
Summary :
Double modular redundancy (DMR) is to execute an operation twice and detect a soft error by comparing the duplicated operation results. The soft error is corrected by re-executing necessary operations. The re-execution requires error-free input data and registers are needed to store such necessary error-free data. In this paper, a method to minimize the required number of registers is proposed where an appropriate subgraph partitioning of operation nodes are searched. In addition, using the proposed register minimization method, a minimization of the area of functional units and registers required to implement the DMR design is proposed.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E105-A No.3 pp.530-539
- Publication Date
- 2022/03/01
- Publicized
- 2021/09/01
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2021VLP0015
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Yuya KITAZAWA
Saitama University
Kazuhito ITO
Saitama University
Keyword
Latest Issue
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Yuya KITAZAWA, Kazuhito ITO, "Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 3, pp. 530-539, March 2022, doi: 10.1587/transfun.2021VLP0015.
Abstract: Double modular redundancy (DMR) is to execute an operation twice and detect a soft error by comparing the duplicated operation results. The soft error is corrected by re-executing necessary operations. The re-execution requires error-free input data and registers are needed to store such necessary error-free data. In this paper, a method to minimize the required number of registers is proposed where an appropriate subgraph partitioning of operation nodes are searched. In addition, using the proposed register minimization method, a minimization of the area of functional units and registers required to implement the DMR design is proposed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021VLP0015/_p
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@ARTICLE{e105-a_3_530,
author={Yuya KITAZAWA, Kazuhito ITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design},
year={2022},
volume={E105-A},
number={3},
pages={530-539},
abstract={Double modular redundancy (DMR) is to execute an operation twice and detect a soft error by comparing the duplicated operation results. The soft error is corrected by re-executing necessary operations. The re-execution requires error-free input data and registers are needed to store such necessary error-free data. In this paper, a method to minimize the required number of registers is proposed where an appropriate subgraph partitioning of operation nodes are searched. In addition, using the proposed register minimization method, a minimization of the area of functional units and registers required to implement the DMR design is proposed.},
keywords={},
doi={10.1587/transfun.2021VLP0015},
ISSN={1745-1337},
month={March},}
Copy
TY - JOUR
TI - Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 530
EP - 539
AU - Yuya KITAZAWA
AU - Kazuhito ITO
PY - 2022
DO - 10.1587/transfun.2021VLP0015
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2022
AB - Double modular redundancy (DMR) is to execute an operation twice and detect a soft error by comparing the duplicated operation results. The soft error is corrected by re-executing necessary operations. The re-execution requires error-free input data and registers are needed to store such necessary error-free data. In this paper, a method to minimize the required number of registers is proposed where an appropriate subgraph partitioning of operation nodes are searched. In addition, using the proposed register minimization method, a minimization of the area of functional units and registers required to implement the DMR design is proposed.
ER -
English
