IEICE TRANSACTIONS on Fundamentals
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects
Summary :
Statistical wafer-level characteristic variation modeling offers an attractive method for reducing the measurement cost in large-scale integrated (LSI) circuit testing while maintaining test quality. In this method, the performance of unmeasured LSI circuits fabricated on a wafer is statistically predicted based on a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in the wafers. However, actual wafers can exhibit discontinuous variations that are systematically caused by the manufacturing environment, such as shot dependence. In this paper, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into systematic discontinuous and global components to improve estimation accuracy. An evaluation performed using an industrial production test dataset indicates that the proposed method effectively reduces the estimation error for an entire wafer by over 36% compared with conventional methods.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E107-A No.1 pp.96-104
- Publication Date
- 2024/01/01
- Publicized
- 2023/07/19
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2023KEP0010
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Systems)
- Category
Authors
Takuma NAGAO
Nara Institute of Science and Technology
Tomoki NAKAMURA
Sony Semiconductor Manufacturing Corporation
Masuo KAJIYAMA
Sony Semiconductor Manufacturing Corporation
Makoto EIKI
Sony Semiconductor Manufacturing Corporation
Michiko INOUE
Nara Institute of Science and Technology
Michihiro SHINTANI
Kyoto Institute of Technology
Keyword
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Takuma NAGAO, Tomoki NAKAMURA, Masuo KAJIYAMA, Makoto EIKI, Michiko INOUE, Michihiro SHINTANI, "Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects" in IEICE TRANSACTIONS on Fundamentals,
vol. E107-A, no. 1, pp. 96-104, January 2024, doi: 10.1587/transfun.2023KEP0010.
Abstract: Statistical wafer-level characteristic variation modeling offers an attractive method for reducing the measurement cost in large-scale integrated (LSI) circuit testing while maintaining test quality. In this method, the performance of unmeasured LSI circuits fabricated on a wafer is statistically predicted based on a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in the wafers. However, actual wafers can exhibit discontinuous variations that are systematically caused by the manufacturing environment, such as shot dependence. In this paper, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into systematic discontinuous and global components to improve estimation accuracy. An evaluation performed using an industrial production test dataset indicates that the proposed method effectively reduces the estimation error for an entire wafer by over 36% compared with conventional methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023KEP0010/_p
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@ARTICLE{e107-a_1_96,
author={Takuma NAGAO, Tomoki NAKAMURA, Masuo KAJIYAMA, Makoto EIKI, Michiko INOUE, Michihiro SHINTANI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects},
year={2024},
volume={E107-A},
number={1},
pages={96-104},
abstract={Statistical wafer-level characteristic variation modeling offers an attractive method for reducing the measurement cost in large-scale integrated (LSI) circuit testing while maintaining test quality. In this method, the performance of unmeasured LSI circuits fabricated on a wafer is statistically predicted based on a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in the wafers. However, actual wafers can exhibit discontinuous variations that are systematically caused by the manufacturing environment, such as shot dependence. In this paper, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into systematic discontinuous and global components to improve estimation accuracy. An evaluation performed using an industrial production test dataset indicates that the proposed method effectively reduces the estimation error for an entire wafer by over 36% compared with conventional methods.},
keywords={},
doi={10.1587/transfun.2023KEP0010},
ISSN={1745-1337},
month={January},}
Copy
TY - JOUR
TI - Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 96
EP - 104
AU - Takuma NAGAO
AU - Tomoki NAKAMURA
AU - Masuo KAJIYAMA
AU - Makoto EIKI
AU - Michiko INOUE
AU - Michihiro SHINTANI
PY - 2024
DO - 10.1587/transfun.2023KEP0010
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E107-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2024
AB - Statistical wafer-level characteristic variation modeling offers an attractive method for reducing the measurement cost in large-scale integrated (LSI) circuit testing while maintaining test quality. In this method, the performance of unmeasured LSI circuits fabricated on a wafer is statistically predicted based on a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in the wafers. However, actual wafers can exhibit discontinuous variations that are systematically caused by the manufacturing environment, such as shot dependence. In this paper, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into systematic discontinuous and global components to improve estimation accuracy. An evaluation performed using an industrial production test dataset indicates that the proposed method effectively reduces the estimation error for an entire wafer by over 36% compared with conventional methods.
ER -
English
