Pipelined ADPCM Compression for HDR Synthesis on an FPGA

Masahiro NISHIMURA; Taito MANABE; Yuichiro SHIBATA

doi:10.1587/transfun.2023VLP0017

Pipelined ADPCM Compression for HDR Synthesis on an FPGA

Masahiro NISHIMURA, Taito MANABE, Yuichiro SHIBATA

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This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E107-A No.3 pp.531-539

Publication Date: 2024/03/01

Publicized: 2023/08/31

Online ISSN: 1745-1337

DOI: 10.1587/transfun.2023VLP0017

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: VLSI Design Technology and CAD

Authors

Masahiro NISHIMURA
  Nagasaki University
Taito MANABE
  Nagasaki University
Yuichiro SHIBATA
  Nagasaki University

Keyword

FPGA, HDR synthesis, image compression

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Masahiro NISHIMURA, Taito MANABE, Yuichiro SHIBATA, "Pipelined ADPCM Compression for HDR Synthesis on an FPGA" in IEICE TRANSACTIONS on Fundamentals, vol. E107-A, no. 3, pp. 531-539, March 2024, doi: 10.1587/transfun.2023VLP0017.
Abstract: This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023VLP0017/_p

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@ARTICLE{e107-a_3_531,
author={Masahiro NISHIMURA, Taito MANABE, Yuichiro SHIBATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Pipelined ADPCM Compression for HDR Synthesis on an FPGA},
year={2024},
volume={E107-A},
number={3},
pages={531-539},
abstract={This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.},
keywords={},
doi={10.1587/transfun.2023VLP0017},
ISSN={1745-1337},
month={March},}

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TY - JOUR
TI - Pipelined ADPCM Compression for HDR Synthesis on an FPGA
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 531
EP - 539
AU - Masahiro NISHIMURA
AU - Taito MANABE
AU - Yuichiro SHIBATA
PY - 2024
DO - 10.1587/transfun.2023VLP0017
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E107-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2024
AB - This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.
ER -