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IEICE TRANSACTIONS on Fundamentals

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations

Koki ITO, Kazushi KAWAMURA, Yutaka TAMIYA, Masao YANAGISAWA, Nozomu TOGAWA

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Summary :

As seen in stream data processing, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M,N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers (MUXs). However, the number of required MUXs increases too much as the input/output byte widths increase. It is known that partitioning a MUX network leads to reducing the number of MUXs. In this paper, we firstly pick up a multi-layered MUX network, which is generated by repeatedly partitioning a MUX network into a collection of single-layered MUX networks. We show that the multi-layered MUX network is equivalent to the barrel shifter from which redundant MUXs and wires are removed, and we prove that the number of required MUXs becomes the smallest among MUX-network-partitioning based field-data extractors. Next, we propose a rotator-based MUX network for a field-data extractor, which is based on reading out a particular data in an input register to a rotator. The byte width of the rotator is the same as its output register and hence we no longer require any extra wires nor MUXs. By rotating the input data appropriately, we can finally have a right-ordered data into an output register. Experimental results show that a multi-layered MUX network reduces the number of required gates to construct a field-data extractor by up to 97.0% compared with the one using a naive approach and its delay becomes 1.8ns-2.3ns. A rotator-based MUX network with a control circuit also reduces the number of required gates to construct a field-data extractor by up to 97.3% compared with the one using a naive approach and its delay becomes 2.1ns-2.9ns.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.4 pp.1015-1028
Publication Date
2017/04/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E100.A.1015
Type of Manuscript
PAPER
Category
VLSI Design Technology and CAD

Authors

Koki ITO
  Waseda University
Kazushi KAWAMURA
  Waseda University
Yutaka TAMIYA
  the Fujitsu Laboratories Ltd.
Masao YANAGISAWA
  Waseda University
Nozomu TOGAWA
  Waseda University

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