IEICE TRANSACTIONS on Fundamentals
Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher
Summary :
This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption/decryption in a single clock cycle. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low-latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.1 pp.149-157
- Publication Date
- 2017/01/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E100.A.149
- Type of Manuscript
- Special Section PAPER (Special Section on Cryptography and Information Security)
- Category
Authors
Ville YLI-MÄYRY
Tohoku University
Naofumi HOMMA
Tohoku University
Takafumi AOKI
Tohoku University
Keyword
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Ville YLI-MÄYRY, Naofumi HOMMA, Takafumi AOKI, "Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher" in IEICE TRANSACTIONS on Fundamentals,
vol. E100-A, no. 1, pp. 149-157, January 2017, doi: 10.1587/transfun.E100.A.149.
Abstract: This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption/decryption in a single clock cycle. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low-latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.149/_p
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@ARTICLE{e100-a_1_149,
author={Ville YLI-MÄYRY, Naofumi HOMMA, Takafumi AOKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher},
year={2017},
volume={E100-A},
number={1},
pages={149-157},
abstract={This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption/decryption in a single clock cycle. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low-latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.},
keywords={},
doi={10.1587/transfun.E100.A.149},
ISSN={1745-1337},
month={January},}
Copy
TY - JOUR
TI - Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 149
EP - 157
AU - Ville YLI-MÄYRY
AU - Naofumi HOMMA
AU - Takafumi AOKI
PY - 2017
DO - 10.1587/transfun.E100.A.149
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2017
AB - This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption/decryption in a single clock cycle. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low-latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.
ER -
English
