IEICE TRANSACTIONS on Fundamentals
AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures
Summary :
The increasing demand on scalability and reusability of system-on-chip design as well as the decoupling between computation and communication has motivated the growth of the Network-on-Chip (NoC) paradigm in the last decade. In NoC-based systems, the computational resources (i.e. IPs) communicate with each other using a network infrastructure. Many works have focused on the development of NoC architectures and routing mechanisms, while the interfacing between network and associated IPs also needs to be considered. In this paper, we present a novel efficient AXI (AMBA eXtensible Interface) compliant network adapter for NoC architectures, which is named an AXI-NoC adapter. The proposed network adapter achieves high communication throughput of 20.8Gbits/s and consumes 4.14mW at the operating frequency of 650MHz. It has a low area footprint (952 gates, approximate to 2,793µm2 with CMOS 45nm technology) thanks to its effective hybrid micro-architectures and with zero latency thanks to the proposed mux-selection method.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.8 pp.1650-1660
- Publication Date
- 2017/08/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E100.A.1650
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Xuan-Tu TRAN
VNU University of Engineering and Technology, a member university of Vietnam National University
Tung NGUYEN
RMIT
Hai-Phong PHAN
VNU University of Engineering and Technology, a member university of Vietnam National University
Duy-Hieu BUI
VNU University of Engineering and Technology, a member university of Vietnam National University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Xuan-Tu TRAN, Tung NGUYEN, Hai-Phong PHAN, Duy-Hieu BUI, "AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures" in IEICE TRANSACTIONS on Fundamentals,
vol. E100-A, no. 8, pp. 1650-1660, August 2017, doi: 10.1587/transfun.E100.A.1650.
Abstract: The increasing demand on scalability and reusability of system-on-chip design as well as the decoupling between computation and communication has motivated the growth of the Network-on-Chip (NoC) paradigm in the last decade. In NoC-based systems, the computational resources (i.e. IPs) communicate with each other using a network infrastructure. Many works have focused on the development of NoC architectures and routing mechanisms, while the interfacing between network and associated IPs also needs to be considered. In this paper, we present a novel efficient AXI (AMBA eXtensible Interface) compliant network adapter for NoC architectures, which is named an AXI-NoC adapter. The proposed network adapter achieves high communication throughput of 20.8Gbits/s and consumes 4.14mW at the operating frequency of 650MHz. It has a low area footprint (952 gates, approximate to 2,793µm2 with CMOS 45nm technology) thanks to its effective hybrid micro-architectures and with zero latency thanks to the proposed mux-selection method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.1650/_p
Copy
@ARTICLE{e100-a_8_1650,
author={Xuan-Tu TRAN, Tung NGUYEN, Hai-Phong PHAN, Duy-Hieu BUI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures},
year={2017},
volume={E100-A},
number={8},
pages={1650-1660},
abstract={The increasing demand on scalability and reusability of system-on-chip design as well as the decoupling between computation and communication has motivated the growth of the Network-on-Chip (NoC) paradigm in the last decade. In NoC-based systems, the computational resources (i.e. IPs) communicate with each other using a network infrastructure. Many works have focused on the development of NoC architectures and routing mechanisms, while the interfacing between network and associated IPs also needs to be considered. In this paper, we present a novel efficient AXI (AMBA eXtensible Interface) compliant network adapter for NoC architectures, which is named an AXI-NoC adapter. The proposed network adapter achieves high communication throughput of 20.8Gbits/s and consumes 4.14mW at the operating frequency of 650MHz. It has a low area footprint (952 gates, approximate to 2,793µm2 with CMOS 45nm technology) thanks to its effective hybrid micro-architectures and with zero latency thanks to the proposed mux-selection method.},
keywords={},
doi={10.1587/transfun.E100.A.1650},
ISSN={1745-1337},
month={August},}
Copy
TY - JOUR
TI - AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1650
EP - 1660
AU - Xuan-Tu TRAN
AU - Tung NGUYEN
AU - Hai-Phong PHAN
AU - Duy-Hieu BUI
PY - 2017
DO - 10.1587/transfun.E100.A.1650
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2017
AB - The increasing demand on scalability and reusability of system-on-chip design as well as the decoupling between computation and communication has motivated the growth of the Network-on-Chip (NoC) paradigm in the last decade. In NoC-based systems, the computational resources (i.e. IPs) communicate with each other using a network infrastructure. Many works have focused on the development of NoC architectures and routing mechanisms, while the interfacing between network and associated IPs also needs to be considered. In this paper, we present a novel efficient AXI (AMBA eXtensible Interface) compliant network adapter for NoC architectures, which is named an AXI-NoC adapter. The proposed network adapter achieves high communication throughput of 20.8Gbits/s and consumes 4.14mW at the operating frequency of 650MHz. It has a low area footprint (952 gates, approximate to 2,793µm2 with CMOS 45nm technology) thanks to its effective hybrid micro-architectures and with zero latency thanks to the proposed mux-selection method.
ER -
English
