IEICE TRANSACTIONS on Fundamentals
Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents
Summary :
This paper presents a measurement-domain intra prediction coding framework that is compatible with compressive sensing (CS)-based image sensors. In this framework, we propose a low-complexity intra prediction algorithm that can be directly applied to measurements captured by the image sensor. We proposed a structural random 0/1 measurement matrix, embedding the block boundary information that can be extracted from the measurements for intra prediction. Furthermore, a low-cost Very Large Scale Integration (VLSI) architecture is implemented for the proposed framework, by substituting the matrix multiplication with shared adders and shifters. The experimental results show that our proposed framework can compress the measurements and increase coding efficiency, with 34.9% BD-rate reduction compared to the direct output of CS-based sensors. The VLSI architecture of the proposed framework is 9.1 Kin area, and achieves the 83% reduction in size of memory bandwidth and storage for the line buffer. This could significantly reduce both the energy consumption and bandwidth in communication of wireless camera systems, which are expected to be massively deployed in the Internet of Things (IoT) era.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2869-2877
- Publication Date
- 2017/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E100.A.2869
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Jianbin ZHOU
Waseda University
Dajiang ZHOU
Waseda University
Li GUO
Waseda University
Takeshi YOSHIMURA
Waseda University
Satoshi GOTO
Waseda University
Keyword
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Jianbin ZHOU, Dajiang ZHOU, Li GUO, Takeshi YOSHIMURA, Satoshi GOTO, "Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents" in IEICE TRANSACTIONS on Fundamentals,
vol. E100-A, no. 12, pp. 2869-2877, December 2017, doi: 10.1587/transfun.E100.A.2869.
Abstract: This paper presents a measurement-domain intra prediction coding framework that is compatible with compressive sensing (CS)-based image sensors. In this framework, we propose a low-complexity intra prediction algorithm that can be directly applied to measurements captured by the image sensor. We proposed a structural random 0/1 measurement matrix, embedding the block boundary information that can be extracted from the measurements for intra prediction. Furthermore, a low-cost Very Large Scale Integration (VLSI) architecture is implemented for the proposed framework, by substituting the matrix multiplication with shared adders and shifters. The experimental results show that our proposed framework can compress the measurements and increase coding efficiency, with 34.9% BD-rate reduction compared to the direct output of CS-based sensors. The VLSI architecture of the proposed framework is 9.1 Kin area, and achieves the 83% reduction in size of memory bandwidth and storage for the line buffer. This could significantly reduce both the energy consumption and bandwidth in communication of wireless camera systems, which are expected to be massively deployed in the Internet of Things (IoT) era.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2869/_p
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@ARTICLE{e100-a_12_2869,
author={Jianbin ZHOU, Dajiang ZHOU, Li GUO, Takeshi YOSHIMURA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents},
year={2017},
volume={E100-A},
number={12},
pages={2869-2877},
abstract={This paper presents a measurement-domain intra prediction coding framework that is compatible with compressive sensing (CS)-based image sensors. In this framework, we propose a low-complexity intra prediction algorithm that can be directly applied to measurements captured by the image sensor. We proposed a structural random 0/1 measurement matrix, embedding the block boundary information that can be extracted from the measurements for intra prediction. Furthermore, a low-cost Very Large Scale Integration (VLSI) architecture is implemented for the proposed framework, by substituting the matrix multiplication with shared adders and shifters. The experimental results show that our proposed framework can compress the measurements and increase coding efficiency, with 34.9% BD-rate reduction compared to the direct output of CS-based sensors. The VLSI architecture of the proposed framework is 9.1 Kin area, and achieves the 83% reduction in size of memory bandwidth and storage for the line buffer. This could significantly reduce both the energy consumption and bandwidth in communication of wireless camera systems, which are expected to be massively deployed in the Internet of Things (IoT) era.},
keywords={},
doi={10.1587/transfun.E100.A.2869},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2869
EP - 2877
AU - Jianbin ZHOU
AU - Dajiang ZHOU
AU - Li GUO
AU - Takeshi YOSHIMURA
AU - Satoshi GOTO
PY - 2017
DO - 10.1587/transfun.E100.A.2869
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - This paper presents a measurement-domain intra prediction coding framework that is compatible with compressive sensing (CS)-based image sensors. In this framework, we propose a low-complexity intra prediction algorithm that can be directly applied to measurements captured by the image sensor. We proposed a structural random 0/1 measurement matrix, embedding the block boundary information that can be extracted from the measurements for intra prediction. Furthermore, a low-cost Very Large Scale Integration (VLSI) architecture is implemented for the proposed framework, by substituting the matrix multiplication with shared adders and shifters. The experimental results show that our proposed framework can compress the measurements and increase coding efficiency, with 34.9% BD-rate reduction compared to the direct output of CS-based sensors. The VLSI architecture of the proposed framework is 9.1 Kin area, and achieves the 83% reduction in size of memory bandwidth and storage for the line buffer. This could significantly reduce both the energy consumption and bandwidth in communication of wireless camera systems, which are expected to be massively deployed in the Internet of Things (IoT) era.
ER -
English
