IEICE TRANSACTIONS on Fundamentals
Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier
Summary :
Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. An 8×8 multiplier design is implemented by employing the carry-maskable adder and the compressor. Compared with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption by between 47.3% and 56.2% and critical path delay by between 29.9% and 60.5%, depending on the required accuracy. Its silicon area was also 44.6% smaller. In addition, results from two image processing applications demonstrate that the quality of the processed images can be controlled by the proposed multiplier design.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.12 pp.2244-2253
- Publication Date
- 2018/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E101.A.2244
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Tongxin YANG
Fukuoka University
Tomoaki UKEZONO
Fukuoka University
Toshinori SATO
Fukuoka University
Keyword
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Tongxin YANG, Tomoaki UKEZONO, Toshinori SATO, "Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2244-2253, December 2018, doi: 10.1587/transfun.E101.A.2244.
Abstract: Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. An 8×8 multiplier design is implemented by employing the carry-maskable adder and the compressor. Compared with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption by between 47.3% and 56.2% and critical path delay by between 29.9% and 60.5%, depending on the required accuracy. Its silicon area was also 44.6% smaller. In addition, results from two image processing applications demonstrate that the quality of the processed images can be controlled by the proposed multiplier design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2244/_p
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@ARTICLE{e101-a_12_2244,
author={Tongxin YANG, Tomoaki UKEZONO, Toshinori SATO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier},
year={2018},
volume={E101-A},
number={12},
pages={2244-2253},
abstract={Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. An 8×8 multiplier design is implemented by employing the carry-maskable adder and the compressor. Compared with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption by between 47.3% and 56.2% and critical path delay by between 29.9% and 60.5%, depending on the required accuracy. Its silicon area was also 44.6% smaller. In addition, results from two image processing applications demonstrate that the quality of the processed images can be controlled by the proposed multiplier design.},
keywords={},
doi={10.1587/transfun.E101.A.2244},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2244
EP - 2253
AU - Tongxin YANG
AU - Tomoaki UKEZONO
AU - Toshinori SATO
PY - 2018
DO - 10.1587/transfun.E101.A.2244
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2018
AB - Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. An 8×8 multiplier design is implemented by employing the carry-maskable adder and the compressor. Compared with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption by between 47.3% and 56.2% and critical path delay by between 29.9% and 60.5%, depending on the required accuracy. Its silicon area was also 44.6% smaller. In addition, results from two image processing applications demonstrate that the quality of the processed images can be controlled by the proposed multiplier design.
ER -
English
