VHDL Design of a SpaceFibre Routing Switch

Alessandro LEONI; Pietro NANNIPIERI; Luca FANUCCI

doi:10.1587/transfun.E102.A.729

Open Access
VHDL Design of a SpaceFibre Routing Switch

Alessandro LEONI, Pietro NANNIPIERI, Luca FANUCCI

Full Text Views

61

Cite this

Free PDF (319.9KB)

Summary :

The technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no standardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1Gbps. However, while several implementations of the SpaceFibre IP already exist, its Network Layer is still at experimental level. This article describes the architecture of an implemented SpaceFibre Routing Switch and provides synthesis results for common FPGAs.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.5 pp.729-731

Publication Date: 2019/05/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E102.A.729

Type of Manuscript: LETTER

Category: VLSI Design Technology and CAD

Authors

Alessandro LEONI
  University of Pisa
Pietro NANNIPIERI
  University of Pisa
Luca FANUCCI
  University of Pisa

Keyword

SpaceFibre, SpaceWire, RoutingSwitch, satellite networks, FPGA

Cite this

Copy

Alessandro LEONI, Pietro NANNIPIERI, Luca FANUCCI, "VHDL Design of a SpaceFibre Routing Switch" in IEICE TRANSACTIONS on Fundamentals, vol. E102-A, no. 5, pp. 729-731, May 2019, doi: 10.1587/transfun.E102.A.729.
Abstract: The technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no standardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1Gbps. However, while several implementations of the SpaceFibre IP already exist, its Network Layer is still at experimental level. This article describes the architecture of an implemented SpaceFibre Routing Switch and provides synthesis results for common FPGAs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.729/_p

Copy

@ARTICLE{e102-a_5_729,
author={Alessandro LEONI, Pietro NANNIPIERI, Luca FANUCCI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VHDL Design of a SpaceFibre Routing Switch},
year={2019},
volume={E102-A},
number={5},
pages={729-731},
abstract={The technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no standardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1Gbps. However, while several implementations of the SpaceFibre IP already exist, its Network Layer is still at experimental level. This article describes the architecture of an implemented SpaceFibre Routing Switch and provides synthesis results for common FPGAs.},
keywords={},
doi={10.1587/transfun.E102.A.729},
ISSN={1745-1337},
month={May},}

Copy

TY - JOUR
TI - VHDL Design of a SpaceFibre Routing Switch
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 729
EP - 731
AU - Alessandro LEONI
AU - Pietro NANNIPIERI
AU - Luca FANUCCI
PY - 2019
DO - 10.1587/transfun.E102.A.729
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2019
AB - The technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no standardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1Gbps. However, while several implementations of the SpaceFibre IP already exist, its Network Layer is still at experimental level. This article describes the architecture of an implemented SpaceFibre Routing Switch and provides synthesis results for common FPGAs.
ER -